Xilinx, Inc.

Abu K Eghan

Richard C Li

Lan H Hoang

Qi Lin

Xin X Wu

An integrated circuit device is described. In particular, the integrated circuit comprises a substrate comprising active devices; a plurality of metal layers formed over the substrate, the plurality of metal layers being separated by insulating layers; a plurality of vias enabling connections to the active devices of the substrate; a contact pad support structure defining an opening in a metal layer of the plurality of metal layers and being coupled to an interconnect line; and a contact pad formed over the contact pad support structure. A method of implementing a contact pad in an integrated circuit is also disclosed.

Integrated circuit and method of implementing a contact pad in an integrated circuit

A pad pattern of a die includes first and second sets of elongated pads. The first set of elongated pads is interleaved with the second set of elongated pads. Each of the elongated pads has a bond pad area and a probe pad. Each bond pad area has a first constant width along a substantial portion thereof. Similarly, each probe pad area has a second constant width along a substantial portion thereof. The first constant width is greater than the second constant width. Each elongated pad in the first set has a first orientation. Similarly, each elongated pad in the second set has a second orientation, opposite the first orientation.

Semiconductor die with high density offset-inline bond arrangement

A semiconductor flipchip package includes a central cavity area on the first major side for receiving a flipchip die therein. The package substrate is substantially made from a single material that serves as the support and stiffener and provides within the cavity floor all the connecting points for flipchip interconnection to the silicon die. The integral cavity wall serves as a stiffener member of the package and provides the required mechanical stability of the whole arrangement without the need for a separate stiffener material to be adhesively attached. The cavity walls may contain extra routing metallization to create bypass capacitors to enhance electrical performance. Optional methods to cover the silicon die enhance thermal performance of the package.

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San Jose, CA, United States of America

Abu K Eghan