National Semiconductor Corporation

Abu-Hena Mostafa Kamal

Jitendra Mohan

Ramsin Michael Ziazadeh

Laurence Douglas Lewicki

Arlo Jame Aude

Yongseon Koh

Christopher S Blair

Amjad T Obeidat

Devnath Varadarajan

Nick S Argenti

A double-sampled pipeline analog-to-digital conversion (ADC) system and method in which latching of the intrastage digital quantization signals occurs approximately midway the leading and trailing edges of the clock signals.

Pipelined analog-to-digital converter with mid-sampling comparison

An analog signal gain controller and equalizer with an increased signal bandwidth for reducing intersymbol interference (ISI) within a digital data signal.

Combined analog signal gain controller and equalizer

A circuit with low noise and reduced offset that feeds an input of an opamp with a programmable feedback resistor that provides variable gain settings. Input biasing currents are varied using control bits that are also used to adjust the gain. When the input signal is small (gain at higher setting), a minimum bias current is provided to source the input voltage swing. This scheme reduces the noise and offset generated by the lower transconductance of a biasing transistor while maintaining a constant SNR and fixed offset even in the presence of relatively small input swings. Also, when the input signal is large (gain at lower setting), a maximum bias current can be provided to accommodate the relatively large input swing level. Although the overall noise and offset current are increased for large input swings, the overall SNR and offset is maintained for relatively lower input swings.

Apparatus and method for employing gain dependent biasing to reduce offset and noise in a current conveyor type amplifier

An operational amplifier circuit with improved feedback factor is provided that includes an input impedance, an operational amplifier, and a current conveyor. The input impedance is operable to receive an input signal. The operational amplifier comprises an inverting input node, a non-inverting input node, and an output node. The operational amplifier is operable to generate an output signal at the output node based on the input signal. The current conveyor is coupled between the input impedance and the inverting input node of the operational amplifier. The current conveyor is operable to provide a low impedance to the input impedance and a high impedance to the operational amplifier.

Operational amplifier circuit with improved feedback factor

A low power analog equalizer is disclosed that provides up to twenty decibels (20 dB) of alternating current gain in a single stage of analog signal equalization. The analog equalizer comprises an operational amplifier coupled to two half circuits. Each half circuit comprises an impedance network capable of receiving an analog input voltage and generating a current signal that is inversely proportional to frequency, a current steering digital to analog converter capable of adjusting the gain of the operational amplifier, and a transistor and an amplifier coupled in a cascode configuration to create a low impedance node at the output of the impedance network. The analog equalizer is fabricated with 0.18 micron CMOS technology and operates at 1.8 volts.

Low power analog equalizer with current mode digital to analog converter

A low power analog equalizer is disclosed that provides up to twenty decibels (20 dB) of alternating current gain in a single stage of analog signal equalization. The analog equalizer comprises an operational amplifier coupled to two half circuits. Each half circuit comprises an impedance network capable of receiving an analog input voltage and generating a current signal that is inversely proportional to frequency, a variable resistor capable of adjusting the gain of the operational amplifier, and a transistor and an amplifier coupled in a cascode configuration to create a low impedance node at the output of the impedance network. The analog equalizer is fabricated with 0.18 micron CMOS technology and operates at 1.8 volts.

Low power analog equalizer with variable op-amp gain

A process for forming self-aligned cobalt silicide layers on an MOS transistor structure that reduces the risk of creating cobalt silicide bridges between source/drain regions and silicon (e.g. amorphous or polysilicon) gates. The process includes the use of an optimized argon sputter etch surface preparation step prior to cobalt layer deposition. The argon sputter etch step utilizes a DC bias of less than &minus;278 volts in order to insure that backsputtering of silicon onto gate sidewall spacers by the argon ions is minimized. Preferred argon etch sputter steps use a DC bias of less than &minus;80 volts, have a native silicon dioxide etch rate of no more than 5 angstroms per minute and target 20 to 60 angstroms of native silicon dioxide removal. Also provided is a process for preparing the surface of an MOS transistor or structure for subsequent cobalt layer deposition and cobalt salicide formation that includes use of an argon sputter etch process with a DC bias of less than &minus;278 volts.

Process for the formation of cobalt salicide layers employing a sputter etch surface preparation step

Process for the formation of a polysilicon layer with a controlled, small silicon grain size that includes first providing a semiconductor substrate (such as a silicon wafer), followed by the formation of a silicon dioxide layer (such as a gate silicon dioxide layer) on the semiconductor substrate. Next, an amorphous silicon layer is deposited on the silicon dioxide layer. The amorphous silicon layer can be deposited using LPCVD at a temperature in the range of 520&deg; C. to 560&deg; C. and a pressure in the range of 150 mTorr to 250 mTorr. Next, a plurality of silicon crystallites are formed in the amorphous silicon layer by subjecting it to a first RTA cycle at a temperature in the range of 750&deg; C. to 850&deg; C. for a time period of 30 seconds to 90 seconds and a temperature ramp rate of at least 50&deg; C. per second. Finally, the amorphous silicon layer with silicon crystallites is subjected to at least one additional thermal cycle, thereby growing the silicon crystallites into small silicon grains and forming a polysilicon layer with controlled, small silicon grain size.

Method for the formation of a polysilicon layer with a controlled, small silicon grain size during semiconductor device fabrication

Process for forming a boron-doped silicon gate layer underlying a cobalt silicide layer that reduces the risk of grooving and agglomeration of cobalt silicide layer, as well as boron penetration into a gate oxide layer. The process includes providing a PMOS transistor structure that includes an N-well on a P-type silicon substrate, a gate oxide layer and a silicon gate layer. Next, a cobalt layer is deposited on the PMOS transistor structure, which is then subjected to a first thermal treatment to form a bilayer CoSi/silicon stack structure. After removing unreacted cobalt, boron dopant (BF,or B,) and nitrogen ions (N,) are implanted into the bilayer CoSi/silicon stack structure. The bilayer CoSi/silicon stack structure, implanted boron and implanted nitrogen are then subjected to second thermal treatment to form a CoSi,layer on the silicon gate layer and to thermally activate the implanted boron. Also included is a process where a PMOS transistor structure that includes an N-well on a P-type silicon substrate, a gate oxide layer and a silicon gate layer is first provided, followed by the implantation of nitrogen into the silicon gate layer. Next, a cobalt layer is deposited on the PMOS transistor structure, which is then subjected to a first thermal treatment to form a bilayer CoSi/silicon stack structure. After removing unreacted cobalt, boron is implanted into the bilayer CoSi/silicon stack structure. The bilayer CoSi/silicon stack structure and implanted boron and implanted nitrogen are then subjected to second thermal treatment to form a CoSi,layer and to thermally activate the implanted boron.

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Santa Clara, CA, United States of America

Abu-Hena Mostafa Kamal