Intel Corporation

Abram M Detofsky

David Shia

Joe F Walczyk

John Michael Peterson

James G Maveety

John C Johnson

Michael L Rutigliano

Todd P Albertson

James Edward Neeb

Todd R Coons

Jin Pan

Arun Krishnamoorthy

Chukwunenye S Nnebe

Brett D Grossman

Sasha N Oster

Pooya Tadayon

Sankaran M Menon

Rolf H Kuehnis

Tak Ming Mak

Jin Yang

Mohanraj Prabhugoud

Ronald K Minemier

Evan M Fledell

Brett E Klehn

Rehan M Sheikh

Dinia P Kitendaugh

Andrew J Hoitink

Mustapha Amadu Abdulai

Asifur Rahman

Mohsen Fazlian

Embodiments described herein may be related to apparatuses, processes, and techniques related to incorporating photonics integrated circuitry into a base die, the base die including an optical interconnect at a bottom of the base die to transmit and to receive light signals from outside the base die. The top of the base die includes one or more electrical connectors that are electrically coupled with the photonics integrated circuitry. The base die may be referred to as the photonics die. A system-on-a-chip (SOC) may be electrically coupled with and stacked onto the top of the photonics die. Other embodiments may be described and/or claimed.

Stackable photonics die with direct optical interconnect

Embodiments described herein may be related to apparatuses, processes, and techniques related to active optical plugs used to cover optical connectors of a photonics package to protect the connectors. The active optical plugs may also be used to perform testing of the photonics package, including generating light to be sent to the photonics package and to detect light received from the photonics package as part of the test protocol. This allows testing the optical connection and the photonics package, without exposing the optical connections of the package to damage from dust or physical contact. Other embodiments may be described and/or claimed.

Active optical plug to optically or electrically test a photonics package

A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.

Converged test platforms and processes for class and system testing of integrated circuits

Embodiments of the present disclosure provide techniques and configurations for a package testing system. In some embodiments, the system may comprise a printed circuit board (PCB), including one or more sensors disposed adjacent to a corner of the PCB to face a package to be tested, to detect an electrical edge of the package. The PCB may include a contactor array disposed to face respective interconnects of the package. The system may further include a controller coupled with the one or more sensors, to process an input from the one or more sensors, to identify the electrical edge of the package, and initiate an adjustment of a position of the PCB relative to the package, based at least in part on the electrical edge of the package, to substantially align contacts of the contactor array with the respective interconnects of the package. Other embodiments may be described and/or claimed.

Package testing system and method with contact alignment

An optical spectral analyzer for measuring an optical multi-channel signal by separating the multi-channel signal and measuring a plurality of single-channel signals simultaneously. The spectral analyzer can include a demultiplexer configured to receive the multi-channel signal. The multi-channel signal can be a multi-channel wavelength range. The demultiplexer can separate the multi-channel signal into the plurality of single-channel signals including a first single-channel signal and a second single-channel signal. The spectral analyzer can include a plurality of optical paths. The plurality of optical paths can include a plurality of respective detectors for measuring an optical power of the respective single-channel signals. The detectors can convert the optical power of the respective single-channel signals to corresponding electrical signals. In some examples, the spectral analyzer includes a controller configured to obtain the plurality of respective electrical signals simultaneously to correspondingly detect the optical power of the multi-channel signal across the multi-channel wavelength range.

Increased processing efficiency for optical spectral analyzers

The disclosed systems, devices, and methods may provide for wireless testing of devices and, in particular, wireless testing of semiconductor devices comprising integrated circuits, memory, and logic circuitry that can be present on a wafer. The semiconductor devices can be tested for functional defects by applying one or more test patterns to the semiconductor devices. Further, for devices under test that do not have built-in wireless connectivity (for example, those that do not have a built-in Bluetooth low-energy engine), the disclosure describes systems and methods that the devices under test can use for external wireless connectivity (e.g., an external board having Bluetooth low-energy) on the low-bandwidth interface. In one example embodiment, for high-bandwidth scan testing, wireless connectivity modules (such as those implementing WiFi or WiGig) are described, which can be used to meet the bandwidth requirements of the one or more tests.

Systems and methods for wireless device testing

A thermal controller includes a thermal control interface to receive test data from an automated test equipment (ATE) system and dynamically adjust a target setpoint temperature based on the data and a dynamic thermal controller to receive the target setpoint temperature from the thermal control interface and control a thermal actuator based on the target setpoint temperature.

Integrated circuit test temperature control mechanism

In accordance with one aspect of the present description, an interface between an integrated circuit device and a test controller for testing the integrated circuit device includes a plurality of boards coupled together. In one embodiment, the test interface includes a plurality of interchangeable auxiliary boards, each having test circuitry, which may be coupled to a primary board and reused as appropriate to test various integrated circuits. Other aspects are described.

Integrated circuit testing architecture

Methods and structures for testing a microelectronic packaging structure/device are described. Those methods may include placing a device in a floating carrier, wherein the floating carrier is coupled to a socket housing by pin dowels disposed in four corners of the socket housing, and wherein at least two actuating motors are disposed within the socket housing, and micro adjusting the device by utilizing a capacitive coupled or a fiber optic alignment system wherein a maximum measured capacitance or maximum measured intensity between alignment structures disposed in the socket housing and alignment package balls disposed within the device indicate optimal alignment of the device. Methods further include methods for active co-planarity detection through the use of a capacitive-coupled techniques.

Micro positioning test socket and methods for active precision alignment and co-planarity feedback

A mechanism is described for facilitating optical testing of a device under test (DUT) using a testing mechanism having multiple testing paths according to one embodiment. A method of embodiments of the invention may include facilitating, via a loopback path, optical testing of the DUT in a loopback configuration. The loopback configuration may allow for looping between one or more transmitters and one or more receivers of the DUT. The method may further include facilitating, via a spectral path, spectral measurements relating to the DUT.

Mechanism for facilitating an optical instrumentation testing system employing multiple testing paths

Provided are a method and a system, in which a first device aligns a chip to a socket along a first axis. A second device aligns the chip to the socket along a second axis, and a third device aligns the chip to the socket along a plane formed by the first axis and a third axis. Also provided is a system comprising a first optical element, and a second optical element, where a first elastic element is coupled to the first optical element, and a second elastic element is coupled to the second optical element, and where the first elastic element is aligned to the second elastic element via elastic coupling.

Method and apparatus for an optical interconnect system

A method includes providing an integrated circuit (IC) having a plurality of oscillators at distributed locations in the IC, determining a respective rate of oscillation of each of the oscillators, and detecting variations in local temperature in the IC based on the determined rates of oscillation. Other embodiments are described and claimed.

Growing community of inventors

Tigard, OR, United States of America

Abram M Detofsky