Agere Systems Inc.

Abraham Prasad

David Allen Brown

Narender R Vangati

Mauricio Calle

Stephen Miller

Prachi Kale

A processor having a packet processing order maintenance feature includes classification circuitry operative to identify for each of a plurality of packets received in the processor a corresponding packet flow identifier, control circuitry operatively coupled to the classification circuitry, and at least one operational unit operatively coupled to the control circuitry. The control circuitry is operative to direct one or more packets having a given packet flow identifier to the operational unit(s) in a manner that maintains a desired function call sequencing over the one or more packets having the given packet flow identifier for one or more order-dependent processing tasks in the processor.

Processor with packet processing order maintenance based on packet flow identifiers

A processing system includes a processing device and a host processor operatively coupled to the processing device via a system bus, and implements a scatter gather data transfer technique. The host processor is configurable to control the transfer of information to or from scattered or non-contiguous memory locations in a memory associated with the processing device, utilizing a data structure comprising a single descriptor. An information transfer bandwidth of the system bus is thereby more efficiently utilized than if a separate descriptor were used for transfer of information involving each of the non-contiguous memory locations.

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Austin, TX, United States of America

Abraham Prasad