International Business Machines Corporation

Globalfoundries Inc.

Abraham Mathews

Donald W Plass

Jente Benedict Kuang

Fadi Hikmat Gebara

Gregory J Fredeman

Kenneth J Reyer

John Edward Barth, Jr

Peter Juergen Klim

Vinod Ramadurai

Saiful Islam

Tuhin Mahmud

Jethro C Law

Geoffrey Wang

Trong V Luong

Aspects of the invention include obtaining one or more feature values that define an architecture design of a memory array and implementing a machine learning model to obtain a predicted power, performance, and area (PPA) of the memory array based on the one or more features. The predicted PPA output by the machine leaning model is assessed based on predefined PPA goals. A design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.

Integrated circuit development using machine learning-based prediction of power, performance, and area

Embodiments include a method, memory system and a device for the operating a bit-line sensing circuit for bias-controlled bit-line sensing, the embodiments include an input for receiving a single-ended local bit-line signal, a pass device having a first terminal coupled to the input and a second terminal connected to a global bit-line node, The embodiments also include a first inverter having an input connected to the global bit-line node, a header circuit coupled to the first inverter and a first direct current (DC) bias circuit, and a footer circuit coupled to the first inverter and a second DC bias circuit. The embodiments include a second gated inverter having an input coupled to an output of the first inverter.

Bias-controlled bit-line sensing scheme for eDRAM

A driver circuit and associated techniques include managing voltage driving an electronic device. An input signal having a first voltage level is received. Processes may perform level shifting of the first voltage level to a second voltage level. The second voltage level may be clamped, for instance, but a diode circuit. The second output voltage level may be programmable, as may be current and resistance levels of the driver circuit.

Dynamic high voltage driver with adjustable clamped output level

A single-ended input sense amplifier uses a pass device to couple the input local bit-line to a global bit-line evaluation node. The sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit-line evaluation node. The output of the second inverter is selectively coupled to the global bit-line evaluation node in response to a control signal, so that when the pass device is active, the local bit line charges or discharges the global bit-line evaluation node without being affected substantially by a state of the output of the second inverter. When the control signal is in the other state, the cross-coupled inverter forms a latch. An internal output control circuit of the second inverter interrupts the feedback provided by the second inverter in response to the control signal.

Gated-feedback sense amplifier for single-ended local bit-line memories

A method of operation of a high-voltage word-line driver circuit for a memory device prevents any single transistor of the driver from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.

Dynamic cascode-managed high-voltage word-line driver circuit

A single-ended low-swing power-savings mechanism is provided. The mechanism comprises a precharge device that turns off in an evaluation phase and a first biasing device is always on. Within the mechanism, a strength of a keeper device is changed to a first level in response to an input of the second biasing device being at a first voltage level. Within the mechanism the strength of the keeper device is changed to a second level in response to the input of the second biasing device being at a second voltage level. Responsive to receiving a (precharged voltage level read data line signal, a precharged voltage level of the first node falls faster when the keeper device is weakened to a first level. The keeper device turns on in response to receiving a LOW signal and pulls up the voltage at the first node so that a HIGH signal is output.

Single-ended low-swing power-savings mechanism with process compensation

A high-voltage word-line driver circuit for a memory device uses cascode devices to prevent any single transistor of the driver circuit from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.

A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90&#xb0; out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.

Peak power reduction methods in distributed charge pump systems

Dual frequency divider having phase-shifted inputs and outputs

A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.

Switched-capacitor charge pumps

A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.

A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

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Austin, TX, United States of America

Abraham Mathews