Cadence Design Systems, Inc.

Abner Luis Panho Marciano

Fabiano Cruz Peixoto

Craig Franklin Deaton

Matheus Nogueira Fonseca

Ronalu Augusta Nunes Barcelos

The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.

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Belo Horizonte-Minas Gerais, Belize

Abner Luis Panho Marciano