Cadence Design Systems, Inc.

Abner Luis Panho Marciano

Fabiano Cruz Peixoto

Raquel Lara Dos Santos Pereira

Matheus Nogueira Fonseca

Adriana Cassia Rossi De Almeida Braz

Thamara Karen Cunha Andrade

Rodrigo Fonseca Rocha Soares

Laiz Lipiainen Santos

Breno Rodrigues Guimarães

Guilherme Seminotti Braga

Rafael Gontijo Hamdan

Bruno Andrade Pereira

Hudson Dyele Oliveira

Caio Texeira Campos

Rodolfo Santos Teixeira

Breno Rodrigues Guimares

In the described examples, a model impact monitor can include an electronic design automation (EDA) manager that communicates with a plurality of EDA programs, wherein each EDA program generates a model set for a register-transfer level (RTL) design comprising a list of RTL operations. The model impact monitor can also include an adaptive model interface that records changes to the RTL operations of the RTL design and measures a change in performance characteristics of each of the plurality of EDA programs based on a respective one of the changes in the RTL operations of the RTL design.

Adaptive model interface for a plurality of EDA programs

Disclosed are techniques for implementing formal verification of an electronic design. These techniques identify a target property for verification in a hierarchical electronic design that has a plurality of hierarchies and perform hierarchical synthesis on a hierarchy or a portion thereof in the plurality of hierarchies while black-boxing a remaining portion of the hierarchical electronic design. Cone of influence (COI) data that is relevant to the target property may be determined at least by extracting the cone of influence data from a hierarchically synthesized hierarchy or portion of the hierarchy or the portion thereof. At least the cone of influence data may be forwarded to a formal engine that uses the cone of influence data to verify the target property.

Methods, systems, and computer program product for verifying an electronic design

Disclosed are techniques for enhancing formal verification with counter acceleration for electronic designs. These techniques identify at least a portion of an electronic design including a counter having a current counter value and intercept next counter values transmitted to the counter with a counter abstraction module. These techniques further determine whether to accelerate the counter from the current counter value to an engine synthesized next counter value, rather than to an original next counter value based at least in part on a set of critical values. The counter is accelerated from the current counter value to the engine synthesized next counter value when the counter abstraction module determines to accelerate the counter.

Methods, systems, and articles of manufacture for enhancing formal verification with counter acceleration for electronic designs

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Belo Horizonte, Brazil

Abner Luis Panho Marciano