Intel Corporation

Abirami Prabhakaran

Dheeraj R Subbareddy

Eugene Gorbatov

David A Koufaty

Ganapati Srinivasa

Scott D Hahn

Paul Brett

Eliezer Weissmann

Andrew J Herdrich

Alon Naveh

Paolo L Narvaez

Gaurav Khanna

Mishali Naik

Inder M Sodhi

Russell Jerome Fenger

Andrew D Henroid

Bret L Toll

Jason W Brandt

Ravishankar Iyer

Stephen Anthony Fischer

Michael Mishaeli

Ashish V Choubal

Hisham Shafi

Rinat Rappoport

Nagabhushan Chitlur

Oron Lenz

Sanjeev S Sahagirdar

Bryant E Bigbee

Russel J Fenger

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method for booting a heterogeneous system and presenting a symmetric core view

An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.

Apparatus and method for intelligently powering heterogeneous processor components

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Apparatus and method for heterogeneous processors mapping to virtual cores

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Hetergeneous processor apparatus and method

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

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Hillsboro, OR, United States of America

Abirami Prabhakaran