Xilinx, Inc.

Abid Karumannil

Vishal K Jain

Sumit Nagpal

Kumar S S Vemuri

Arun Kumar Patil

Anitha Barri

Anil K Martha

Anusha Perla

Venkataraju Koppada

Sairam K M Menon

Scheduling work of a machine learning application includes instantiating kernel objects by a computer processor in response to input of kernel definitions. Each kernel object is of a kernel type indicating a compute circuit. The computer processor generates a graph in a memory. Each node represents a task and specifies an assignment of the task to one or more of the kernel objects, and each edge represents a data dependency. Task queues are created in the memory and assigned to queue tasks represented by the nodes. Kernel objects are assigned to the task queues, and the tasks are enqueued by threads executing the kernel objects, based on assignments of the kernel objects to the task queues and assignments of the tasks to the kernel objects. Tasks are dequeued by the threads, and the compute circuits are activated to initiate processing of the dequeued tasks.

Scheduling processing of machine learning tasks on heterogeneous compute circuits

Examples herein describe a method for a compiler and hardware-abstraction-layer architecture for a programmable integrated circuit (IC). In one embodiment, a method for mapping and porting a neural network to an integrated circuit (IC) is disclosed. The method includes receiving a network description of the neural network; generating a framework independent network graph based on the network description; performing a plurality of back-end operations on the network graph to generate an execution sequence vector; and configuring the IC based on the execution sequence vector.

Compiler and hardware abstraction layer architecture for a neural network accelerator

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Malappuram, India

Abid Karumannil