Atomera Incorporated

Atomera Incorporation

Abid Husain

Hideki Takeuchi

Yi-Ann Chen

A CMOS image sensor may include a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first semiconductor chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice

A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip including image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip in a stack. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice

A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip comprising image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip together in a stack. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice

A CMOS image sensor may include an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.

CMOS image sensor including pixels with read circuitry having a superlattice

A method for making a CMOS image sensor may include forming an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.

Method for making CMOS image sensor including pixels with read circuitry having a superlattice

A method for making a CMOS image sensor may include forming a plurality of laterally adjacent photodiodes on a semiconductor substrate having a first conductivity types by forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, forming a first well around a periphery of the retrograde well also having the second conductivity type, and forming a second well within the retrograde well having the first conductivity type. Furthermore, first and second superlattices may be respectively formed overlying each of the first and second wells, with each of the first and second superlattices comprising a plurality of stacked groups of layers, and each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk

A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk

A CMOS image sensor may include a first semiconductor chip including image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions and a superlattice channel extending between the source and drain regions. The superlattice channel may include a plurality of stacked groups of layers, each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. Each transistor may further include a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice

A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate. Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the second conductivity type, and a second well within the retrograde well having the first conductivity type. Each photodiode may further include first and second superlattices respectively overlying each of the first and second wells. Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk

A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a superlattice on the semiconductor substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The image sensor may further include a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

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San Jose, CA, United States of America

Abid Husain