Intel Corporation

Abid Asghar

Peter D MacWilliams

Gary A Solomon

George R Hayek

Nicholas D Wade

Kirby S Hallenbeck

Joseph A Skupnjak

James R Donnell

An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.

Arbitration signaling mechanism to prevent deadlock guarantee access

An erasable programmable logic device which includes a programmable AND memory array and a macrocell processing the output of the AND array allows product term sharing/allocation by adjacent macrocells. Two groups of four product terms each are coupled to each macrocell, wherein the OR'ing of each group of four product terms is each coupled to a multiplexor. One group is also coupled to a previously adjacent macrocell and the second group is coupled to a subsequently adjacent macrocell. A third and fourth multiplexor accept four product terms from each of the adjacent macrocells and the output of the four multiplexors are coupled to an OR gate. When a multiplexor is activated, it couples each grouping of four product terms to the OR gate and the output of the OR gate is coupled to an I/O circuit which emulates combinatory and sequential logic circuits. By selecting appropriate multiplexors each eight product term macrocell is capable of processing 0, 4, 8, 12 or 16 product terms. An alternative embodiment has three groupings of product terms wherein only two of the groupings are shared by adjacent macrocells.

Product term sharing/allocation in an EPROM array

An improved architecture for an EPROM PAL utilizing two bit lines is disclosed. The drains of the EPROM cells of a given column of an array are coupled together to a first bit line. The first line is coupled to a sensing circuit. The sources of the EPROM cells are coupled together to a second bit line which is then coupled through a current limiting transistor. The gate of the transistor is coupled to the first bit line to receive a feedback signal for controlling the current on the bit lines. The current limiting feature provides for shorter transition periods between 'on' and 'off' states which results in an improved speed performance of the device.

Current limited epld array

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Sacramento, CA, United States of America

Abid Asghar