Imec Vzw

Abhitosh Vais

Liesbeth Witters

Yves Mols

The present disclosure provides an HBT that includes (i) a semiconductor support layer; at least four wall structures side-by-side on the support layer; (iii) a semiconductor collector-material ridge structure disposed on the support layer between two adjacent wall structures of the at least four wall structures; (iv) a semiconductor base-material layer, wherein a first part of the base-material layer is disposed on a first region of the ridge structure and a second part of the base-material layer is disposed across the wall structures, wherein the base-material layer is supported by the wall structures; (v) a semiconductor emitter-material layer disposed on the first part of the base-material layer; (vi) a base contact layer disposed on the second part of the base-material layer; an emitter contact layer disposed on the emitter-material layer; and (viii) a collector contact layer disposed on a second region of the ridge structure.

Low parasitic Cheterojunction bipolar transistor

A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

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Heverlee, Belgium

Abhitosh Vais