Intel Corporation

Abhishek Venkatesh

Prasoonkumar Surti

Michael Apodaca

Travis T Schluessler

Murali Ramadoss

Karthik Vaidyanathan

Joydeep Ray

Abhishek R Appu

Devan Burke

Altug Koker

Jonathan Kennedy

Slawomir Grajewski

John G Gierach

Kai Xiao

Atsuo Kuwahara

Tomer Bar-On

Hugues Labbe

Tomasz Janczak

Sameer Kp

Subramaniam M Maiyuran

Kamal Sinha

Nikos Kaburlasos

Linda L Hurd

Wenyin Fu

Bhushan M Borole

Balaji Vembu

Saurabh Sharma

Andrew T Lauritzen

David M Cimini

Louis Feng

Elmoustapha Ould-Ahmed-Vall

Vasanth Ranganathan

Sanjeev S Jahagirdar

Guei-Yuan Lueh

Kiran Chand Veernapu

David M Puffer

John H Feit

Aravindh V Anantaraman

Jacek Kwiatkowski

Pattabhiraman K

Josh B Mastronarde

Eric J Hoekstra

Eric J Asperheim

Ankur N Shah

Aditya Navale

Peter L Doyle

Gabor Liktor

Jeffery S Boles

Philip R Laws

Vamsee Vardhan Chivukula

Robert B Taylor

Eriko Nurvitadhi

Selvakumar Panneer

James A Valerio

Amit Bleiweiss

Thomas F Raoux

Oguz Hasan Elibol

Dhawal Srivastava

Anil Thomas

Gokce Keskin

Adam Z Leibel

Daniel Walsh

Satyajit Sarangi

Hashem Hashemi

Pruthvi Gowda Thorehosur Appajigowda

Nishant Patel

Huma Abidi

Jaikrishnan Menon

Rama S B Harihara

Tomer Bar On

Subramanian Maiyuran

Travis T Schluesser

Jeffrey S Boles

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Controlling coarse pixel size from a stencil buffer

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

Compute optimization mechanism for deep neural networks

Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.

Synergistic temporal anti-aliasing and coarse pixel shading technology

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Hybrid low power homogenous grapics processing units

One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value. The resolve can be a stenciled resolve that automatically bypasses execution of a pixel shader for pixels having clear color data.

Leveraging control surface fast clears to optimize 3D operations

Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology

Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

Anti-aliasing adaptive shader with pixel tile coverage raster rule system, apparatus and method

An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.

Mutli-frame renderer

An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.

Asynchronous execution mechanism

The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.

Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer

A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

Frequent data value compression for graphics processing units

Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

GPU mixed primitive topology type processing

Growing community of inventors

Hillsboro, OR, United States of America

Abhishek Venkatesh