Arm Limited

Abhishek Raja

Michael Filippo

Yasuo Ishii

Huzefa Moiz Sanjeliwala

Miles Robert Dooley

Albin Pierrick Tonnerre

Alexander Cole Shulyak

Michael David Achenbach

Guillaume Bolbenes

James David Dundas

Geoffray Lacourba

Glen Andrew Harris

Chris Abernathy

Kelvin Domnic Goveas

Natalya Bondarenko

Barry Duane Williamson

Bipin Prasad Heremagalur Ramaprasad

Balaji Vijayan

Stefano Ghiggini

Devin S Lafford

Paolo Monti

Zachary Allen Kingsbury

Anton Smekalov

Andrew Brookfield Swaine

William Elton Burky

Houdhaifa Bouzguarrou

Ian Michael Caulfield

Joseph Michael Pusdesris

Klas Magnus Bruce

Luca Nassi

Robert Greg McDonald

Michael Brian Schinzler

Andrew John Turner

Karthik Sundaram

Alexander Alfred Hornung

Matthew Andrew Rafacz

Adrian Montero

Vincenzo Consales

Timothy Hayes

Alexander Donald Charles Chadwick

Nicholas Andrew Plante

Jason Lee Setter

Jungsoo Kim

Rakesh Shaji Lal

Vasu Kudaravalli

Yohan Fernand Fargeix

Nicholas Andrew Pfister

Kias Magnus Bruce

David Gum Lim

Eric Charles Quinnell

Rania Hussein Hassan Mameesh

Abdel Hadi Moustafa

Anoop Ramachandra Iyer

Li Ma

Fabian Gruber

Kamil Garifullin

Sharmila Shridhar

A data processing apparatus is provided. Cache circuitry caches data, the data being indexed according to execution contexts of processing circuitry. Receive circuitry receives invalidation requests each referencing a specific execution context in the execution contexts. Invalidation circuitry invalidates at least some of the data in the cache circuitry and filter circuitry filters the invalidation requests based on at least one condition and, when the condition is met, causes the invalidation circuitry to invalidate the data in the cache circuitry.

Filtering invalidation requests

There is provided an apparatus, a method, a system, a chip containing product, and a medium. The apparatus comprises a first storage structure to store a first set of data items, the first storage structure comprising a first transaction queue to store first transaction data to track fulfilment of outstanding first transaction requests. The apparatus is also provided with a second storage structure. The first storage structure is responsive to a received request for a given data item, to issue a first transaction request for the given data item to the second storage structure, and for a stage of fulfilment of the first transaction request, to omit storage of information relating to the first transaction request in the first transaction queue and to delegate the maintenance of at least some information relating to the stage of fulfilment of the first transaction request to the second storage structure.

Fulfilment of transaction requests

Apparatuses, methods, systems, and chip-containing products are disclosed, which relate to an arrangement comprising a level N cache level and a level M cache level, where M is greater than N. The level N cache level comprises a plurality of linefill slots and performs a slot allocation procedure in response to a lookup miss in dependence on a linefill slot occupancy criterion. The slot allocation procedure comprises allocation of an available slot of the plurality of slots to a pending linefill request generated in response to the lookup miss. The level N cache level effects a modification of the slot allocation procedure in dependence on the linefill slot occupancy criterion and is responsive to the linefill slot occupancy criterion being fulfilled to cause a linefill delegation action to be instructed to the level M cache level.

Linefill delegation in a cache hierarchy

There is provided an apparatus, system, chip-containing product, method, and storage medium. The apparatus comprises memory access circuitry responsive to one or more types of memory access request, to retrieve specified data items from memory. The apparatus is also provided with local storage circuitry configured to store at least some of the retrieved data items. The local storage circuitry is N-way associative, and N is greater than 1. The apparatus is also provided with control circuitry responsive to an indication that an access request signalled to the local storage circuitry relating to an accessed data item corresponds to a predefined type of memory access request, to implement a restrictive access policy in relation to the accessed data item in the local storage circuitry. The restrictive access policy excludes at least one step of accessing an excluded subset of ways of the local storage circuitry.

Access requests to local storage circuitry

An apparatus is provided. Delegable memory accesses are offloaded to be performed by an external processing apparatus, whereas non-delegable memory accesses are performed locally. Nonetheless, an ordering requirement may still be enforced between them. The apparatus comprises tracking circuitry to maintain tracking information related to delegable memory accesses separately from tracking information related to non-delegable memory accesses. Order enforcement circuitry may enforce an ordering requirement between a non-delegable memory access and a delegable memory access based on a lookup of the tracking information.

Order enforcement for delegable memory accesses

There is provided an apparatus comprising decoder circuitry to decode store instructions and load instructions. The apparatus includes decoder circuitry to decode store instructions and load instructions. The apparatus also includes prediction circuitry to store load predictions and store predictions. Each load prediction is indexed based on a program counter value of one of the load instructions and comprises information indicative of a predicted store instruction predicted to store data to memory to be subsequently loaded from the memory by that load instruction. Each store prediction is indexed based on the program counter value of one of the store instructions and comprises information indicative of the store instruction being predicted to be indicated as the predicted store instruction in at least one of the plurality of load predictions. Conditions for maintaining the load predictions are different from conditions for maintaining the store predictions.

Storing load predictions

There is provided an apparatus, a method, and a computer readable storage medium. The apparatus comprises memory translation circuitry responsive to receipt of a translation request specifying a first address, to perform a page table walk process to identify a corresponding second address. The apparatus is also provided with control circuitry responsive to receipt of a memory synchronisation occurring subsequent to at least one maintenance operation, to implement a delay before performing the memory synchronisation. The delay continues whilst one or more pending memory accesses affected by the maintenance operation are outstanding. The control circuitry is configured to perform a filtering process to identify candidate page table walk processes affected by the maintenance operation and, for each candidate page table walk, to cancel the candidate page table walk process and to issue a replayed translation request to trigger a replay of the candidate page table walk process.

Memory synchronisation subsequent to a page table walk

An apparatus comprises processing circuitry to issue store operations to store data to a data store and load operations to load data from the data store and a store buffer comprising entries to store entry information corresponding to store operations in advance of the store operations completing. Store buffer lookup circuitry is provided to lookup, in response to a load operation, whether the store buffer contains a corresponding entry corresponding to an older store operation for which target addresses of the load operation and the older store operation satisfy an address comparison condition. The store buffer lookup circuitry is configured to perform store-to-load forwarding in response to the load operation when the corresponding entry is a first type of store buffer entry satisfying a forwarding condition, and delay processing of the load operation when the corresponding entry is a second type of store buffer entry satisfying the forwarding condition.

Store buffer

There is provided an apparatus, medium and method for cache invalidation. The apparatus comprises a cache having a plurality of entries grouped into a plurality of entry sets. Each entry of the plurality of entries identifies an address range having one of a plurality of predetermined address range sizes. The apparatus further comprises cache invalidation circuitry responsive to a cache invalidation request indicating an address invalidation range to trigger invalidation of entries in the cache that overlap the address invalidation range. The cache invalidation circuitry is configured to operate in one of a plurality of invalidation modes based on the address invalidation range and cache occupancy information indicating address range sizes identified by the plurality of entries in the cache. The plurality of invalidation modes comprise: an entry-driven invalidation mode in which the cache invalidation circuitry is configured, for each entry of the plurality of entries and in response to a determination that the address invalidation range overlaps the address range identified by that entry, to invalidate that entry; and an invalidation-range-driven invalidation mode in which the cache invalidation circuitry is configured to generate a set of address range sizes based on the address range sizes indicated in the cache occupancy information and, for each given address range size, to generate one or more cache indexes from the address invalidation range in dependence on the given address range size, each of the cache indexes identifying a corresponding entry set of the plurality of entry sets, and for each corresponding entry set to invalidate entries in dependence on whether the address range identified by those entries overlaps the address invalidation range.

Apparatus and method for cache invalidation

An apparatus is provided for controlling the operating mode of control circuitry, such that the control circuitry may change between two operating modes. In an allocation mode, data that is loaded in response to an instruction is allocated into storage circuitry from an intermediate buffer, and the data is read from the storage circuitry. In a non-allocation mode, the data is not allocated to the storage circuitry, and is read directly from intermediate buffer. The control of the operating mode may be performed by mode control circuitry, and the mode may be changed in dependence on the type of instruction that calls the data, and whether the data may be used again in the near future, or whether it is expected to be used only once.

Controlling data allocation to storage circuitry

There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression. The allocation circuitry is responsive to a frequency of occurrence of memory access instructions addressing the access-sensitive memory meeting a predetermined condition, to suppress the compression whilst the predetermined condition is met.

Compression of entries in a reorder buffer

An apparatus has processing circuitry, load tracking circuitry and load prediction circuitry. It is determined whether tracking information indicates that there is a risk of target data, corresponding to an address of a speculatively-issued load operation which is speculatively issued (bypassing an older operation) based on a prediction determined by the load prediction circuitry, having changed between the target data being loaded for the speculatively-issued load operation and data being loaded for a given older load operation bypassed by the speculatively-issued load operation. If so, independent of whether the addresses of the speculatively-issued load operation and the given older load operation correspond, at least the speculatively-issued load operation is reissued, even when the prediction is correct. This protects against ordering violations.

Apparatus and method with prediction for load operation

Each entry in a cache has type information associated therewith to indicate a type associated with the data item stored in that entry. Lookup circuitry responds to a given lookup request by performing a lookup procedure to determine whether a hit is detected, by default performing the lookup procedure for a given subset of multiple supported types. Invalidation circuitry processes an invalidation request specifying invalidation parameters used to determine an invalidation address range and invalidation type information, in order to invalidate any data items held in the cache storage that are both associated with the invalidation address range and have an associated type that is indicated by the invalidation type information. Whilst processing of the invalidation request is yet to be completed, filtering circuitry performs a filtering operation for a received lookup request, in order to determine, in dependence on an address indication provided by the received lookup request and one or more of the invalidation parameters of the invalidation request, intersection indication data identifying, for a given type in the given subset, whether an intersection is considered to exist between any entries that would be accessed during performance of the lookup procedure for the received lookup request for the given type and any entries that will be invalidated during processing of the invalidation request, and operation of the lookup circuitry is controlled in dependence on the intersection indication data.

Technique for processing lookup requests, in a cache storage able to store data items of multiple supported types, in the presence of a pending invalidation request

An apparatus supports decoding and execution of a bulk memory instruction specifying a block size parameter. The apparatus comprises control circuitry to determine whether the block size corresponding to the block size parameter exceeds a predetermined threshold, and performs a micro-architectural control action to influence the handling of at least one bulk memory operation by memory operation processing circuitry. The micro-architectural control action varies depending on whether the block size exceeds the predetermined threshold, and further depending on the states of other components and operations within or coupled with the apparatus. The micro-architectural control action could include an alignment correction action, cache allocation control action, or processing circuitry selection action.

Control of bulk memory instructions

Circuitry comprises two or more clusters of execution units, each cluster comprising one or more execution units to execute processing instructions; and scheduler circuitry to maintain one or more queues of processing instructions, the scheduler circuitry comprising picker circuitry to select a queued processing instruction for issue to an execution unit of one of the clusters of execution units for execution; in which: the scheduler circuitry is configured to maintain dependency data associated with each queued processing instruction, the dependency data for a queued processing instruction indicating any source operands which are required to be available for use in execution of that queued processing instruction and to inhibit issue of that queued processing instruction until all of the required source operands for that queued processing instruction are available and is configured to be responsive to an indication to the scheduler circuitry of the availability of the given operand as a source operand for use in execution of queued processing instructions; and the scheduler circuitry is responsive to an indication of availability of one or more last awaited source operands for a given queued processing instruction, to inhibit issue by the scheduler circuitry of the given queued processing instruction to an execution unit in a cluster of execution units other than a cluster of execution units containing an execution unit which generated at least one of those last awaited source operands.

Circuitry and method

Growing community of inventors

Austin, TX, United States of America

Abhishek Raja