Intel Corporation

Abhishek R Appu

Joydeep Ray

Altug Koker

Prasoonkumar Surti

Balaji Vembu

Vasanth Ranganathan

Elmoustapha Ould-Ahmed-Vall

Subramaniam M Maiyuran

Kamal Sinha

Travis T Schluessler

Kiran Chand Veernapu

Linda L Hurd

Ankur N Shah

Sanjeev S Jahagirdar

Nicolas C Galoppo Von Borries

Ben J Ashbaugh

Dukhwan Kim

Murali Ramadoss

Nikos Kaburlasos

Wenyin Fu

John Charles Weast

Pattabhiraman K

Varghese George

David M Puffer

John H Feit

Michael S Strickland

Narayan Srinivasa

Karthik Vaidyanathan

Feng Chen

Xiaoming Chen

Aravindh V Anantaraman

Chandrasekaran Sakthivel

Bhushan M Borole

Adam T Lake

Ping Tak Tang

James A Valerio

Sara S Baghsorkhi

Devan Burke

Jacek Kwiatkowski

Mike MacPherson

Eriko Nurvitadhi

Farshad Akhbari

Anbang Yao

Nadathur Rajagopalan Satish

Jeffery S Boles

Jonathan Kennedy

Mike B Macpherson

Lakshminarayanan Striramassarma

Stanley J Baran

Justin E Gottschlich

Rajkishore Barik

Guei-Yuan Lueh

Tsung-Han Lin

Tatiana Shpeisman

Liwei Ma

James M Holland

Hugues Labbe

Josh B Mastronarde

Narayan Biswal

Atsuo Kuwahara

Sang-Hee Lee

Michael Apodaca

Deepak Shashidhar Vembar

Scott R Janus

Kai Xiao

Niranjan L Cooray

Peter L Doyle

Gabor Liktor

Abhishek Venkatesh

Tomer Bar-On

Richmond Hicks

Gokcen Cilingir

Jill MacDonald Boyce

Kun Tian

Changliang Wang

Eric C Samson

Sanu K Mathew

Mark A Anders

Himanshu Kaul

Ingo Wald

John G Gierach

Lidong Xu

Nausheen Ansari

Zhi Hu Wang

Carsten Benthin

Rajesh M Sankaran

Ximin Zhang

Selvakumar Panneer

Daniel Pohl

Christopher J Hughes

Yi-Jen Chiu

Aditya Navale

Zhi Jun Wang

Srikanth Kambhatla

Kunjal ShyamKumar Parikh

Ravishankar Iyer

Jason Daniel Tanner

Thomas A Piazza

Jaydeep P Kulkarni

Sven Woop

For example, one embodiment of an apparatus comprises: ray traversal hardware logic to perform traversal operations to traverse rays through a bounding volume hierarchy (BVH) comprising a plurality of BVH nodes, the ray traversal hardware logic comprising a plurality of traversal storage banks to store traversal data associated with the BVH nodes and/or the rays as the ray traversal hardware logic performs the traversal operations; and a cache comprising a plurality of cache banks to store the traversal data prior to being moved into the traversal storage banks for processing by the ray traversal hardware logic; and an inter-bank interconnect comprising: a point-to-point switch matrix to couple any of the cache banks to any of the traversal storage banks; an arbiter/allocator to control the point-to-point switch matrix to establish a particular group of interconnections between the cache banks and the traversal storage banks in a given clock cycle.

Apparatus and method for routing data from ray tracing cache banks

Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.

Compression for sparse data structures utilizing mode search approximation

Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.

Lossless compression for multisample render targets alongside fragment compression

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

Regional adjustment of render rate

Examples described herein relate to a manner of determining a number of bits to encode compression data. Some examples include: compressing pixel data of a region of pixels in a frame; determining a number of bits associated with at least two partitions; utilizing the determined number of bits to encode residual values generated from the compressing the pixel data; and storing the encoded residual values. In some examples, the at least two partitions comprise a first partition and a second partition. Some examples include: encoding residuals in the first partition using a number of bits associated with the first partition and encoding residuals in the second partition using a number of bits associated with the second partition. Some examples include: determining a distribution of bins of residuals, wherein each different bin represents a number of bits used to encode a residual value and determining a midpoint of a total number of residuals as a bin that stores a residual that is approximately 50 percentile of the total number of residuals of the distribution.

Memory allocation technologies for data compression and de-compression

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

System, apparatus and method for increasing performance in a processor during a voltage ramp

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Dynamic memory reconfiguration

One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

Compute optimizations for low precision machine learning operations

Embodiments are generally directed to memory prefetching in multiple GPU environment. An embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (GPUs) to process data, each of the GPUs including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the GPUs is to prefetch data from the memory to the cache of the GPU; and wherein the prefetcher of a GPU is prohibited from prefetching from a page that is not owned by the GPU or by the host processor.

Prefetch status notification for memory prefetching

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

Systolic arithmetic on sparse data

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

Interconnect fabric link width reduction to reduce instantaneous power consumption

Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

Implicit fence for write messages

Growing community of inventors

El Dorado Hills, CA, United States of America

Abhishek R Appu