Freescale Semiconductor,inc.

Nxp Usa, Inc.

Abhishek Mahajan

Gaurav Goyal

Amol Agarwal

Neha Srivastava

Anurag Jindal

Bipin B Malhan

Sidhartha Taneja

Gaurav Jain

Himanshu Mangal

Sagar Kataria

Mayank Parasrampuria

Amitesh Khandelwal

Anubhav Srivastava

Pratyush Pranav Joshi

Love Gupta

A clock control system for a scan chain generates two clock signals. During a shift phase of a testing mode of the scan chain, one clock signal is an inverted version of the other clock signal. The clock control system provides the clock signal and the inverted clock signal to two different scan flip-flops of the scan chain, respectively. Each of the two scan flip-flops performs a flip-flop operation when the received clock signal transitions from a de-asserted state to an asserted state. Thus, the two flip-flop operations are mutually exclusive during the shift phase. As a result, a dynamic voltage drop across the scan chain during the shift phase is reduced.

Clock control system for scan chains

An integrated circuit (IC), operable in internal and external testing modes (INTEST and EXTEST), includes first and second partitions and a functional path therebetween. The first partition includes a first scan chain, a first multiplexer, and a first flip-flop. The second partition includes a second flip-flop and a second scan chain. The first scan chain generates an EXTEST vector initialization signal, based on an EXTEST scan input signal. The first multiplexer receives an INTEST vector initialization signal and the EXTEST vector initialization signal, and generates a scan input signal. The first flip-flop generates a first output signal based on the scan input signal. The functional path provides a second output signal based on the first output signal. The second flip-flop generates a third output signal based on the second output signal. The second scan chain receives the third output signal and generates a test output signal.

Scan wrapper circuit for integrated circuit

A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.

Signal delay flip-flop cell for fixing hold time violation

A clock multiplexer includes first and second input stages for outputting first and second clock signals, respectively. The first and second input stages each include a flip-flop, a latch and a first logic gate. Reset terminals of the flip-flops receive a select signal based on which the first and second input stages output the first and second clock signals. A second logic gate is connected to the first and second input stages for selectively providing the first and second clock signals as an output clock signal.

Clock multiplexer

A system for generating a gated clock signal includes an AND gate and a clock gating cell. The AND gate receives a reset signal and an input clock signal and generates a clock signal that is provided to a clock input terminal of the clock gating cell. The clock gating cell generates a gated clock signal based on an input signal and the clock signal. Gating the clock input to a latch allows a means for conserving power.

System for generating gated clock signals

A level shifting flip-flop for generating a level-shifted output signal based on an input signal includes a master stage and a slave stage. The slave stage has an integrated level shifting circuit. The slave stage level shifts a signal as it passes through the flip-flop, which eliminates the need of level shifting the signal after it is output from the flip-flop.

Level shifting flip-flop

A clock gating cell for gating clock signals includes a latch circuit, a comparison logic circuit, a first logic circuit, and a second logic circuit. An input signal is provided to the latch circuit. An input clock signal is provided to the first logic circuit. The first logic circuit switches the input clock signal based on a comparison signal generated by the comparison logic circuit, thereby generating a latch clock signal. The latch clock signal switches between a first state and a second state only when the input signal switches between the first state and the second state, thereby preventing power loss of the clock gating cell.

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Chandigarh, India

Abhishek Mahajan