Stmicroelectronics S.r.l.

Stmicroelectronics Pvt. Ltd.

Stmicroelectronics International N.v.

Microsemi Soc Corporation

Abhishek Lal

Marco Pasotti

Promod Kumar

Vikas Rana

Marcella Carissimi

Fabio De Santis

Rajat Kulshrestha

Amit Tandon

Bhawana Singh Nirwan

BharathManoj Manda

A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of Vare to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage Vbelow which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V, wherein Vis chosen such that either both conditions (V&#x3c;V) and (V+V&#x3e;V) or both conditions (V&#x3e;V) and (V&#x2212;V&#x3c;V) are always true.

Power supply glitch detector

According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer.

System and method for a level shifting decoder

According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.

System and method for phase change memory with erase flag cells

An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.

Non-volatile memory device with clustered memory cells

A fail-safe level shifter switching with high speed and operational for a wide range of voltage supply includes a cascode module, and one or more speed enhancer modules. The cascode module receives one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.

Fail-safe high speed level shifter for wide supply voltage range

The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, a pull-up circuit, and a pull down circuit. The negative elevating circuit senses a transition of a logic input signal to generate a control signal. The first pull-up circuit is operatively coupled to this control signal for switching the driver output from a negative voltage to a ground voltage. There is an additional delay module which is configured to provide a delay in the logic input signal. This delayed logic input signal is operatively coupled to the second pull-up stage which takes the output of the driver from GND to VDD. The pull-down circuit is operatively coupled to the negative elevator for controlling a voltage at the driver output to the negative level. The module further comprises a switching circuit that is operatively coupled to the driver output for controlling the passing of a high voltage with high current requirements.

High voltage switch with reduced voltage stress at output stage

An improved binary decoder incorporating a selection circuit that activates a selected output corresponding to a input binary value, and a deselecting circuit coupled to each output that deactivates all other outputs when the selected output is activated. The deselecting circuit arrangement has a single input connected to the selected output and a plurality of outputs each of which is connected to one of the remaining outputs and forces them to the inactive state whenever the selected output is activated.

Growing community of inventors

Faridabad, India

Abhishek Lal