Megachips Corporation

Abhishek Kumar Khare

Shubham Srivastava

Raghavendra R G

Anil Chawda

A high performance phase-locked loop, the device includes a phase frequency detector, a charge pump, a loop filter, a first oscillator having inverters, configured to generate a first current, a second oscillator having a scaled version of the inverters of the first oscillator, a digital to analog converter, configured to generate a second current by multiplying the first current and a frequency code, a voltage to current converter, configured to generate a third current by converting voltage output of the loop filter to current, wherein input current to the second oscillator is sum of the second current and the third current.

High performance PLL based on PVT independent stable oscillator

A high performance equalization method is disclosed for achieving low deterministic jitter across Process, Voltage and Temperature (PVT) for various channel lengths and data rates. The method includes receiving input signal at front end of a receiver upon passing through a channel, generating with an eye-opening monitor circuit a control code based on channel conditions, and equalizing with a continuous-time linear equalization equalizer (CTLE) circuit the input signal based on the control code such that the eye-opening monitor circuit and the CTLE circuit are biased based on their corresponding replica circuits, and the control code is generated in a feedforward configuration.

High performance equalizer achieving low deterministic jitter across PVT for various channel lengths and data rates

A frequency stable oscillator with compensation circuit, the device includes a ring oscillator circuit having S number of stages, a current generator circuit configured to generate a first current, a replica circuit having an inverter with output connected to input, configured to generate a first voltage upon dumping a second current onto the replica circuit, a first operational transconductance amplifier (OTA) with an input as the first voltage, configured to generate a third current and a current mirror circuit configured to generate a fourth current by adding the first current and the third current in a particular ratio M:N, wherein the inverter of the replica circuit is equivalent to a single stage of the ring oscillator circuit and wherein the fourth current is the total current for the ring oscillator circuit and is as close as possible to S times the second current.

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Bengaluru, India

Abhishek Kumar Khare