Cadence Design Systems, Inc.

Abhishek Kanungo

Yonghao Chen

Franz Erich Marschner

Phil Giangarra

Sandeep Pagey

Bijaya Kumar Sahu

Apurva Kalia

Mickey Rodriguez

Amit Kohli

Christer Cederberg

Sulabh Nangalia

A logic simulation electronic design automation (EDA) application, the logic can be configured to receive a circuit design of an integrated circuit (IC) chip, the circuit design comprising an imported module comprising a list of simple immediate assertions (SIAs) for the imported module, wherein the circuit design comprises a first power domain and a second power domain, wherein the first power domain controls a power state of the second power domain and the imported module is assigned to the second power domain. The logic simulation EDA application can be configured to convert, in response to user input, each SIA in the list of SIAs into a respective hybrid deferred assertion (HDA) to form a list of HDAs for the imported module and execute a simulation of the IC chip, and execution of the simulation can include execution of a plurality of time slots for a plurality of simulation cycles.

Hybrid deferred assertion for circuit design

A method and system are provided for automatically creating an implicit literal value in a user defined enumerated data type by inserting an additional literal value, scanning the HDL design files for broken interdependencies or potential incompatibilities with the implicitly defined literal value, and modifying the HDL design files to be in accordance with the implicitly defined literal value while maintaining the semantics of the VHDL language reference model.

Method and system for providing an implicit unknown value to user ENUM data constructs in an HDL system to model power shutoff in simulation

Method and system for providing an implicit unknown value to user enum data constructs in an HDL system to model power shutoff in simulation

A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment, design and verification checksums are calculated for instances of a desired module. The design and verification checksums may be used to further derive hierarchical design and functional checksums. In another embodiment, these checksums are used to merge multiple databases produced by verification runs. In a further embodiment a computing apparatus is provided. The computing apparatus is configured to merge multiple verification databases.

Methods and apparatus for merging coverage for multiple verification and design scenarios

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Nashua, NH, United States of America

Abhishek Kanungo