Stmicroelectronics International N.v.

Adobe, Inc.

Samsung Electronics Co., Ltd.

Stmicroelectronics S.r.l.

Stmicroelectronics Pvt. Ltd.

Infineon Technologies Canada Inc.

Abhishek Jain

Sachin Soni

Ajay Jain

Sanjeev Tagra

Chittoor Parthasarathy

Andrea Mario Veggetti

Ankur Bal

Nitesh Goyal

Shagun Kush

Kallol Chatterjee

Shawn Alan Gaither

Anand Kumar

Nikolaos Barmpalios

Sharad Gupta

Sunil Rathour

Dhananjay L Govekar

Ankit Agarwal

Deepak Kumar Garg

Vobbilisetty Sushant

Nirmal Pandey

Pankaj Rohilla

Samarth Gupta

Mohit Chhabra

Naqushab Neyazee

Vaibhav Garg

Ayush Chaturvedi

Manoj N Kumar

Marco A Zuniga

Amitoj Singh

Carl Dockhorn

Ashutosh Ravindra Joharapurkar

Zhemin Zhang

Niranjan Shivanand Kumbi

Amit Chhabra

Shashank Shekhar

Eric Andrew Kienle

Ajay Awatramani

Tasleem Arif

Amit Srivastava

Ramesh G Karpur

Prakhar Avasthi

Yalong Li

Munwar Khan

Rohan Samsi

Rajan Dahiya

Nitish Maurya

Govind Maheshwari

Varad Arya

Ishani Ghosh

SaurabhKumar Singh

Nikita Kapoor

Jaideep Kumar Vishwakarma

Aman Jindal

Rohit Chaturvedi

Gorav Sharma

Arun Goyal

Ashish Rawat

Supriya Manna

Nibha Sharma

Shobhit Verma

Manu Tiwari

Suraj Somashekara Kumar

Ashutosh Kumar

A circuit that is capable of generating a negative voltage on a negative voltage supply node. The circuit includes a negative voltage generation circuit, an oscillator and an oscillator control signal generator. The negative voltage generation circuit generates a negative voltage on the negative voltage supply node in response to receiving a signal from the oscillator. The negative voltage generated by the negative voltage generation circuit depends upon the frequency of the signal from the oscillator. The oscillator control signal generator controls the frequency of the signal from the oscillator by sensing the negative voltage present on the negative voltage supply node, and by increasing or decreasing the frequency of the signal from the oscillator accordingly. Thus, charge is replenished to the negative voltage supply node to more closely match the drawing of charge from that negative voltage supply node, thereby more accurately generating the negative voltage.

Negative voltage generator

An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multibit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

On chip test architecture for continuous time delta sigma analog-to-digital converter

A method for image capture using artificial intelligence (AI) techniques to generate a user-personalized and noise-corrected final image from a captured image, that includes classifying a noise associated with a lens of an imaging device, preprocessing the captured image based on the classified noise to determine an initial region of interest (ROI), generating a first processed image by inputting the initial ROI and the captured image to a deep learning network, receiving a passive user input corresponding to a portion of a first preview of the first processed image, determining an additional ROI based on the passive user input and the classified noise, generating a second processed image by inputting the second ROI and the captured image to the deep learning network, and generating a user-personalization based noise-corrected final image based on the second processed image.

Method and system operating an imaging system in an image capturing device based on artificial intelligence techniques

A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

Multiplexer with highly linear analog switch

Techniques are disclosed for identifying asides within a document, and detecting a display order of contents based of the identified asides. In a document, an 'aside' represents a content region of the document that is distinct from the main content regions, and may be visually distinguishable from the main content region. In an example, a document is received, where the document lacks identification of asides. The document is analyzed to identify asides within the document. A display order of contents within the document is then determined, based on the identified asides. For example, in the display order, the asides are ordered between two segments of the main content and/or at a beginning or an end of the main content, but may not be ordered to be embedded in between a segment of the main content. The document is displayed in accordance with the display order.

Asides detection in documents

A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.

Sigma-delta analog-to-digital converter circuit with data sharing for power saving

An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

In implementations of systems for role classification, a computing device implements a role system to receive data describing a corpus of text that is associated with a user ID. Feature values of features are generated by a first machine learning model by processing the corpus of text, the features representing questions with respect to the corpus of text and the feature values representing answers to the questions included in the corpus of text. A classification of a role is generated by a second machine learning model by processing the feature values, the classification of the role indicating a relationship of the user ID with respect to a product or service. The role system outputs an indication of the classification of the role for display in a user interface of a display device.

Systems for role classification

Techniques are provided herein for generating improved document summaries that consider the amount of time that has passed since the user last accessed the document. The length of time that has passed since the user has accessed each previous portion of the document is used as a variable to determine how much the summary should focus on each of the previously read sections of the document. When a document is accessed by a user, a relevance score is assigned to content from previously accessed sections of that document, where the relevance score is weighted based on how long ago each of the sections was accessed by the user. Once the various content items of previous sections have been provided relevance scores, selected sentences with the highest relevance scores are fed to a deep learning sequence-to-sequence model is used to build the document summary.

Generating time-based recaps of documents using a deep learning sequence to sequence model

A circuit and methods of operation thereof are provided for robust protection against soft errors. The circuit includes a first set of storage elements coupled to and configured to sample a set of data inputs at a first set of times. The circuit includes a second set of storage elements coupled to and configured to sample the set of data inputs at a second set of times. A first parity generator generates a first parity check for the set of data inputs and a second parity generator generates a second parity check for output of the first set of storage elements. An error correction unit compares the first parity check and the second parity check to detect occurrences of error conditions in the circuit. The error correction unit may control output or operating characteristics of the circuit as a result of error conditions detected.

Robust soft error tolerant multi-bit D flip-flop circuit

In some embodiments, a review application accesses a review file containing a text-based comment describing a change to an object in a design file. The design file is created and editable in a design application different from the review application. The review application determines, from the text-based comment, a tool in the design application configured to implement the change to the object described in the text-based comment. The review application updates the user interface to include a user interface of the tool along with the text-based comment and receives, through the user interface of the tool, a confirmation of applying the change to the object in the design file. The review application further causes the change to the object to be applied to the design file.

Integrated review and revision of digital content

A method of battery management of an electronic device, the electronic device, and a non-transitory computer readable recording medium are provided. The method includes detecting, by the electronic device, that a battery management criterion is met, enabling at least one of a plurality of battery management functions, in response to detecting that the battery management criterion is met, and performing at least one action corresponding to the enabled at least one of the plurality of the battery management functions.

Method and electronic device for enabling at least one battery management function for managing battery usage

A method of processing an image in an electronic device. The method may comprise; obtaining a first image; selecting, based on comparing the first image with a plurality of second images, at least one third image from the plurality of second images, wherein the at least one third image is similar to the first image; identifying an identifier of an image group corresponding to the at least one third image; associating the first image with the identifier of the image group; and notifying, on the device, based on the identifier of the image group, existence of the at least one third image.

Method and system for management and operation over image in a computing system

Growing community of inventors

Delhi, India

Abhishek Jain