International Business Machines Corporation

Applied Materials, Inc.

Globalfoundries Inc.

Stmicroelectronics Gmbh

Abhishek Dube

Viorel C Ontalus

Xuebin Li

Schubert S Chu

Judson Robert Holt

Yi-Chiau Huang

Kevin K Chan

Hua Chung

Kathryn Turner Schonenberg

Keith Howard Tabakman

Zhengmao Zhu

Dominic Joseph Schepis

Errol Antonio C Sanchez

Patricia M Liu

Jinghong Li

Matthew W Stoker

Ashima B Chakravarti

Linda R Black

Flora Fong-Song Chang

Zhiyuan Ye

Dae-Gyu Park

Benjamin Colombeau

Yihwan Kim

Sanjay S Natarajan

Saurabh Chopra

Jophy Stephen Koshy

Geng Wang

David P Thompson

Chengwen Pei

Subramanian Srikanteswara Iyer

Mark Joseph Saly

Babar Ali Khan

Jeffrey W Anthis

Xinyu Bao

Gaurav Thareja

Paul Christian Parries

Ravi Mahendra Todi

Oh-Jung Kwon

Johanes F Swenberg

Ala Moradian

Malcolm J Bevan

Junedong Lee

Gerd Pfeiffer

Eric C Harley

Jessica Sevanne Kachian

Tushar Mandrekar

Eric C T Harley

Sheng-Chin Kung

Joseph S Newbury

Bo Bai

Andy Lo

Jenn-Yue Wang

Chen-Ying Wu

Srividya Natarajan

Alexander Reznicek

Devendra K Sadana

Huilong Zhu

Stephen W Bedell

Nitin K Ingle

Abhijit Basu Mallick

Reinaldo Ariel Vega

Jeffrey Bowman Johnson

Thomas N Adam

Zhengwen O Li

Emre Alptekin

Anthony I Chou

Henry K Utomo

Kartik Bhupendra Shah

Suketu Arun Parikh

Shu-Kwan Danny Lau

Jingmei Liang

Martin Jeffrey Salinas

Tien-Jen Cheng

Steven C H Hung

Brian Hayes Burrows

Zuoming Zhu

Xiaolin C Chen

Richard Omar Collins

Shwu-Jen Jeng

Steven Ware Jones

Toshiyuki Nakagawa

Matthias Bauer

Hasan Munir Nayfeh

Steven C Hung

Kiran V Thadani

Dimitri R Kioussis

Chia Cheng Chin

Enle Choo

Brian Saxton Underwood

Amit Chatterjee

Manjunath Subbanna

Danny D Wang

Jeremy John Kempisty

Rainer Loesing

Desmond J Donegan, Jr

Bei Liu

Pierre Tomasini

Erika R Warrick

Shainish Nellikka

Chandra Mohapatra

The present disclosure relates to methods of correlating zones of processing chambers, and related systems and methods. In one implementation, a method of correlating zones of a processing chamber includes partitioning the processing volume into a plurality of zones along a first direction of the processing volume and a second direction of the processing volume. The second direction intersects the first direction. The plurality of zones have a first zone number (m), and a second zone number (n). The method includes determining a group number. The determining of the group number includes multiplying a first value by a second value. The first value correlates to a first zone number (m) of a plurality of zones and the second value correlates to a second zone number (n) of the plurality of zones. The method includes grouping the zones into groups having a number that is equal to the group number.

Methods of correlating zones of processing chambers, and related systems and methods

Silicon germanium (SiGe)/silicon containing superlattice structures and methods for forming the same are provided. Various embodiments utilize SiGe layers in a SiGe/Si superlattice structure, which include varying concentrations of germanium throughout the layer. For example, in some embodiments, for each SiGe layer there is a core SiGe film with a low Ge content and two thinner SiGe layers or cladding layers positioned on opposing sides of the core SiGe film with each of the SiGe cladding layers having a higher Ge content then the core SiGe film. Various embodiments provide for SiGe layers having a germanium depth profile enabling strained SiGe superlattice deposition on Si{110} substrates.

Graded superlattice structure for gate all around devices

Embodiments generally relate to methods for depositing silicon-phosphorous materials, and more specifically, relate to using silicon-phosphorous compounds in vapor deposition processes (e.g., epitaxy, CVD, or ALD) to deposit silicon-phosphorous materials. In one or more embodiments, a method for forming a silicon-phosphorous material on a substrate is provided and includes exposing the substrate to a deposition gas containing one or more silicon-phosphorous compounds during a deposition process and depositing a film containing the silicon-phosphorous material on the substrate. The silicon-phosphorous compound has the chemical formula [(RHSi)—(RHSi)]PHR', where each instance of R and each instance of R′ are independently an alkyl or a halogen, n is 0, 1, or 2; v is 0, 1, 2, or 3; w is 0, 1, or 2; x is 1, 2, or 3; y is 0, 1, or 2; z is 0, 1, or 2, and where x+y+z=3.

Method for forming silicon-phosphorous materials

A process chamber includes a chamber body having a ceiling disposed above a floor with a chassis and an injector ring disposed therebetween. Upper and lower clamp rings secure the upper and floors, respectively, in place. An upper heating module is coupled to the upper clamp ring above the ceiling. A lower heating module is coupled to the lower clamp ring below the floor.

Epitaxial deposition chamber

Embodiments of the present disclosure generally relate to methods for forming epitaxial layers on a semiconductor device. In one or more embodiments, methods include removing oxides from a substrate surface during a cleaning process, flowing a processing reagent containing a silicon source and exposing the substrate to the processing reagent during an epitaxy process, and stopping the flow of the processing reagent. The method also includes flowing a purging gas and pumping residues from the processing system, stopping the flow of the purge gas, flowing an etching gas and exposing the substrate to the etching gas. The etching gas contains hydrogen chloride and at least one germanium and/or chlorine compound. The method further includes stopping the flow of the at least one compound while continuing the flow of the hydrogen chloride and exposing the substrate to the hydrogen chloride and stopping the flow of the hydrogen chloride.

Method and apparatus for low temperature selective epitaxy in a deep trench

One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.

Selective methods for fabricating devices and structures

A method for the selective formation of epitaxial layers is described herein. In the method, epitaxial layers are deposited to form source and drain regions around a horizontal gate all around (hGAA structure). The method includes co-flowing a combination of chlorinated silicon containing precursors, antimony containing precursors, and n-type dopant precursors. The resulting source and drain regions are selectively grown from crystalline nanosheets or nanowires of the hGAA structure over the non-crystalline gate structure and dielectric layers. The source and drain regions are predominantly grown in a &#x3c;110&#x3e; direction.

Selective low temperature epitaxial deposition process

Embodiments generally relate to methods for depositing silicon-phosphorous materials, and more specifically, relate to using silicon-phosphorous compounds in vapor deposition processes (e.g., epitaxy, CVD, or ALD) to deposit silicon-phosphorous materials. In one or more embodiments, a method for forming a silicon-phosphorous material on a substrate is provided and includes exposing the substrate to a deposition gas containing one or more silicon-phosphorous compounds during a deposition process and depositing a film containing the silicon-phosphorous material on the substrate. The silicon-phosphorous compound has the chemical formula [(RHSi)&#x2014;(RHSi)]PHR', where each instance of R and each instance of R&#x2032; are independently an alkyl or a halogen, n is 0, 1, or 2; v is 0, 1, 2, or 3; w is 0, 1, or 2; x is 1, 2, or 3; y is 0, 1, or 2; z is 0, 1, or 2, and where x+y+z=3.

Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

Gate interface engineering with doped layer

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Integrated CMOS source drain formation with advanced control

Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.

Cap oxidation for FinFET formation

Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

Method of fabricating a semiconductor device having reduced contact resistance

The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Embodiments of the present disclosure enable formation of a source/drain contact with reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

Semiconductor device, method of making a semiconductor device, and processing system

A method of forming a film on a substrate having silicon surfaces and dielectric surfaces includes precleaning the substrate; applying an inhibitor species to the dielectric surfaces; and exposing the substrate to a precursor while maintaining a temperature of less than about 600 degrees Celsius.

Method and apparatus for selective epitaxy

A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

Selective process for source and drain formation

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Fishkill, NY, United States of America

Abhishek Dube