Cisco Technology, Inc.

Abhishek Bhat

Romesh Kumar Nandwana

Kadaba Lakshmikumar

Pavan Kumar Hanumolu

Joseph V Pampanin

Sujit Handanhal Ramachandra

Bibhu Prasad Das

Ajay Bharadwaj

A charge-pump based low dropout (LDO) regulator is provided that overcomes latch-up issues. The LDO regulator is a high PSR low noise LDO regulator that uses a latch-up mitigated charge-pump voltage doubler which includes a N-type metal-oxide-semiconductor field-effect transistor (MOSFET), NMOS, pass transistor. This LDO regulator architecture may be used to provide a very low-noise supply regulated output voltage with high power supply rejection for an on-chip low jitter oscillator. Latch-up is mitigated using control circuitry and a power supply timing sequence. This scheme ensures that parasitic diodes associated with various transistors in the regulator are not forward biased.

Latch-up mitigated charge pump for high power supply rejection low-dropout regulator

A voltage-controlled oscillator (VCO) is disclosed that includes an inductor-capacitor (LC) tank coupled with a first voltage supply node, a pair of cross-coupled transistors that are coupled with the LC tank and coupled with each other at a tail node, and a high-frequency current return path to the first voltage supply node. The high-frequency return path includes a first decoupling capacitor coupled with the first voltage supply node and a second voltage supply node, and a first inductor coupled with the tail node and the second voltage supply node. The first inductor is formed as a first conductive trace and has a quality factor (Q) value of 25 or greater.

Inductive-capacitive voltage-controlled oscillator with increased common-mode impedance

Techniques to reduce or eliminate phase noise and jitter from a noisy clock signal. A method includes generating an electrical clock signal, generating a delayed optical clock signal based on the electrical clock signal, detecting a phase difference between the electrical clock signal and the delayed optical clock signal, and processing, based on the phase difference, the electrical clock signal to obtain a reduced phase noise version of the electrical clock signal.

Clock jitter and spurious tone cancellation system using optical delay

A multi-segment digital-to-time converter is provided. The digital-to-time converter includes a plurality of delay stages arranged in series, and a plurality of local synchronization logic circuits each configured to control an associated delay stage of the plurality of delay stages. Each local synchronization logic circuit provides a digital-to-time converter code and a reset signal to the associated delay stage synchronized to a local input clock and a local output clock of the associated delay stage.

Segmented digital-to-time converter

Presented herein are techniques for implementing a hybrid fractional-N sampling phase locked loop with accurate digital-to-time calibration. A method includes receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator, supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter, supplying an output of the digital-to-time converter to an input of the sampling phase detector, and supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator.

Hybrid fractional-N sampling phase locked loop (PLL) with accurate digital-to-time converter (DTC) calibration

A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as 'average' DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.

Low area equalizer with lane mismatch adaptation for sub-rate receivers

Presented herein are techniques for implementing a differential sub-sampling phase locked loop (PLL). A method includes detecting a common-mode voltage on an output of a differential sub-sampling phase detector operating in the differential sub-sampling phase locked loop, and controlling, based on the common-mode voltage, a duty cycle of a feedback signal of the differential sub-sampling phase locked loop that is fed back to the differential sub-sampling phase detector.

Calibration loop for differential sub-sampling phase detector in sub-sampling phase locked loop

An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.

Frequency tracking loop using a scaled replica oscillator for injection locked oscillators

A multi-port coupled inductor with interference suppression is provided with a first signal port connected to a first resistor port via a first inductor; a second resistor port connected to the first resistor port via a second inductor; a second signal port connected to the second resistor port via a third inductor; a third resistor port connected to the first resistor port via a first resistor; a fourth resistor port connected to the third resistor port via a fourth inductor and to the second resistor port via a second resistor; a third signal port connected to the third resistor port via a fifth inductor; and a fourth signal port connected to the fourth resistor port via a sixth inductor.

Multi-port coupled inductor with interference suppression

A clock generator includes a first phase-locked loop (PLL), a converter circuit, and a second PLL. The first PLL generates an oscillating signal based on a reference signal and outputs a noise signal indicating a noise component of the oscillating signal. The converter circuit produces an electrical signal based on the noise signal. The second PLL receives the electrical signal from the converter circuit at a loop filter of the second PLL and generates a clock signal based on the oscillating signal and the electrical signal.

Phase-locked loop with phase noise cancellation

A voltage controlled oscillator (VCO) is described. The VCO includes a plurality of nodes coupled with a plurality of transistors, and a first inductor-capacitor (LC) tank coupled with a second LC tank. The first LC tank and the second LC tank include a shared inductor structure coupled to the plurality of nodes. The first LC tank and the second LC tank each include a capacitor. The capacitors are each coupled on a first side to a node of the plurality of nodes and on a second side to a respective capacitor in the other LC tank. The first LC tank and the second LC tank are configured to resonate at a fundamental frequency for differential-mode signals, and the first LC tank and the second LC tank are configured to resonate at twice the fundamental frequency for common-mode signals.

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Allentown, PA, United States of America

Abhishek Bhat