Intel Corporation

Abhirupa Layek

Mrittika Ganguli

David Sonnier

Stephen T Palermo

William G Burroughs

Shrikant M Shah

Abhishek Khade

Gage Eads

Sarita Maini

Bradley Chaddick

Edwin Verplanke

Rahul R Shah

Niall D McDonnell

Priya Autee

Rajesh M Sankaran

Reshma Lal

Ren Wang

Jr-Shian Tsai

Sameh Gobriel

Anjali Singhai Jain

Narayan Ranganathan

Rahul C Shah

Nilesh K Jain

Brinda Ganesh

Yipeng Wang

Somnath Paul

Bruce Richardson

Chetan Hiremath

Chih-Jen Chang

Sriram Kabisthalam Muthukumar

Abhijit Davare

Anton Alexandrovich Sorokin

Desmond A Kirkpatrick

John Mangan

Nupur Jain

Niall Mcdonnell

Suvadeep Banerjee

Praveen Mosur

Shaman Narayana

Jaykant B Timbadiya

Nalini Murari

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Dynamic load balancing for multi-core computing environments

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

Hardware queue scheduling for multi-core computing environments

Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

Network layer 7 offload to infrastructure processing unit for service mesh

Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

Hardware offload circuitry

Growing community of inventors

Chandler, AZ, United States of America

Abhirupa Layek