Stmicroelectronics International N.v.

Stmicroelectronics S.a.

Melexis Technologies Sa

Abhirup Lahiri

Nitin Kumar Gupta

Anand Kumar

Nitin Bansal

Gagan Midha

Sebastien Dedieu

Anurag Ramesh Tiwari

Shenjie Wang

Shrestha Bansal

A stabilized oscillator which comprises a ring oscillator with an odd number of inverters. The output of an inverter is driving a capacitor and the input of the a next inverter. A feedback element is configured for generating a first and a second current with a fixed current ratio between both, and for applying the same voltage over the ring oscillator as over a resistor which is connected in parallel with a current compensator. The first current goes through the parallel connection, the second current goes through the ring oscillator. The current compensator is configured such that the ratio of the current through the current compensator and a parasitic current component of the second current is substantially equal to the ratio of the first and second current.

Feedback stabilized ring oscillator

A reference voltage generator circuit includes a circuit that generates a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) current. An output current circuit generates, from the PTAT current, a sink PTAT current sunk from a first node and a source PTAT current sourced to a second node, wherein the sink and source PTAT currents are equal. A resistor is directly connected between the first node and the second node. A divider circuit divides the CTAT voltage to generate a divided CTAT voltage applied to the first node. A voltage at the second node is a fractional bandgap reference voltage equal to a sum of the divided CTAT voltage and a voltage drop across the resistor that is proportional to a resistor current equal to the sink and source PTAT currents.

Fractional bandgap reference voltage generator

A digital low drop-out regulator circuit includes transistor switches that are selectively actuated in response to a comparison of an output voltage at an output node to corresponding tap reference voltages. A dynamic reference voltage correction circuit operates to shift voltage levels of the tap reference voltages in response to a difference between the output voltage at the output node and an input reference voltage.

Digital low drop-out (LDO) voltage regulator with analog-assisted dynamic reference correction

An embodiment circuit includes a first charge pump configured to generate a first current at a first node, and a second charge pump configured to generate a second current at a second node. The circuit further includes an isolation buffer coupled between the first node and the second node and an adder having a first input coupled to the second node. The circuit additionally includes an auxiliary charge pump configured to generate a third current at a second input of the adder, and an oscillator having an input coupled to an output of the adder.

Phase locked loops having decoupled integral and proportional paths

A current mirror circuit provides a current to drive a load. A noise cancelling circuit is provided to keep the load current constant in spite of variations in the supply voltage. The noise cancelling circuit includes an auxiliary current path which branches from the load current path. The length-to-width ratios of transistors of the circuit are selected to provide the desired noise cancellation while maintaining device stability.

Noise canceling current mirror circuit for improved PSR

Disclosed herein is a circuit including a phase frequency detector (PFD) configured to compare phases of an input signal and a feedback signal, and to generate first and second control signals as a function of that comparison. An attenuation circuit includes a capacitor coupled in series between a node and a switching node, and is configured to charge the capacitor and disconnect the switching node from ground based on assertion of the first control signal, and discharge the capacitor and connect the switching node to ground based on assertion of the second control signal.

Charge pump circuit for a phase locked loop

A phase-locked-loop includes a phase-frequency-detector (PFD) comparing phases of an input signal and feedback signal, and generating therefrom control signals. An attenuation circuit in series with the PFD includes a filter between a voltage-controlled-oscillator (VCO) control node and ground. A buffer is coupled to the VCO control node. An impedance network is coupled to the VCO control node and has an impedance element coupled to a first current source so voltage at the VCO control node increases when control signals indicate the phase of the input signal leads the feedback signal, and coupled to a second current source so voltage at the VCO control node decreases when control signals indicate a lagging phase. A VCO is coupled to the VCO control node to generate an output signal, with the phase of the output signal matching the input signal. The feedback signal is based upon the output signal.

A multiple phase oscillator includes a master oscillator that injection locks a first ring oscillator. The free-running frequency of the first ring oscillator is adjustable through a control signal. A second ring oscillator has a same structure as the first ring oscillator and is connected to operate in a free-running mode. The free-running frequency of the second ring oscillator is adjustable through the control signal. A control loop senses the output of the second ring oscillator and adjusts the control signal so that the free-running frequency of the second ring oscillator matches a desired value.

Low-noise multiple phase oscillator

A phase locked loop (PLL) circuit includes a phase comparison circuit configured to compare phase of an input signal to phase of a feedback signal and generate a control signal responsive to the phase comparison and an oscillator circuit configured to generate an output signal at a frequency set by said control signal, where said feedback signal is derived from said output signal. The PLL circuit further operates in a calibration mode of operation wherein the oscillator circuit operates in a frequency locked loop mode to compare frequency of the input signal to frequency of the output signal and center a gain of the oscillator circuit across process, voltage and temperature in response to the frequency comparison. Furthermore, bias current for a charge pump within the phase comparison circuit is calibrated during calibration mode of operation to match a temperature independent reference current.

Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature

According to an embodiment, a circuit includes a first charge pump configured to generate a first current at a first node, a second charge pump configured to generate a second current at a second node, a loop filter coupled between the first and second nodes, the loop filter including a first filter path coupled to the first node, a second filter path coupled to the second node, and an isolation buffer interposed between the first and second filter paths. The second current at the second node is different than the first current at the first node. The circuit further includes an oscillator configured to apply a first gain to an output of the first filter path and a second gain to an output of the second filter path.

Capacitance multiplier and loop filter noise reduction in a PLL

A PTAT circuit includes a first, second, third, and fourth transistors plus a resistor. The first and second transistors have control terminals coupled to each other. The third and fourth transistors have control terminals coupled to each other. The third transistor sources a first current to the first transistor and the fourth transistor sources a second current to the second transistor. The resistor is coupled at a node to the second transistor. A current source circuit sources additional current into the node that is derived from the first and second currents. In one implementation, the additional current is a scaled mirror of the second current. In another implementation, the additional current is a scaled mirror of the sum of the first and second currents. An output current is obtained by mirroring one of the first-third currents. A band-gap output voltage is obtained by applying the additional current across a resistance.

Low power reference generator circuit

A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

Current reused stacked ring oscillator and injection locked divider, injection locked multiplier

A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO.

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Delhi, India

Abhirup Lahiri