Synopsys, Inc.

Abhinav Singla

Rajarshi Mukherjee

Paras Mal Jain

Mahantesh D Narwade

Soumen Ghosh

Mark Roizman

Vijaya V Varkey

Pronay Kumar Biswas

A method of performing static verification of a circuit design that includes a number of circuit blocks, includes, in part, receiving a first model of a first block generated using a first version of a verification tool and having associated therewith data representative of a version number of each of a multitude of verification tests performed by the first version of the tool as well as associated first setup information. In response to the determination that, for each of the of tests performed, the version number of the test to be run on the circuit design is incompatible with the version number of the test performed by the first version of the tool, portions of the first model that were tested with the version number(s) of the test(s) determined to be incompatible with the version number(s) of the test(s) to be run on the circuit design are regenerated.

Multi-machine version independent hierarchical verification

A word-level design model may be loaded into memory. Next, a masking layer may be created which includes objects in the word-level design model that are not used by an IC design analysis system. The masking layer may then be used to provide a reduced block model view on-the-fly to the IC design analysis system.

Generating a reduced block model view on-the-fly

Growing community of inventors

Greater Noida, India

Abhinav Singla