Intel Corporation

Abhinav Pandey

Kiran Pangal

Prashant S Damle

Hanmant Pramod Belgal

Sanjay Rangan

Davide Mantegazza

Dany-Sebastien Ly-Gagnon

Sebastian T Uribe

Arjun Kripanidhi

Hanmant P Belgal

An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.

Apparatus and method for drift cancellation in a memory

Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.

Threshold voltage expansion

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Boise, ID, United States of America

Abhinav Pandey