Qualcomm Incorporated

Abhinav Kothiala

Anand Bhat

Nishi Bhushan Singh

Ashutosh Anand

Praveen Raghuraman

Rajesh Kumar Tiwari

Nikhil Sudhakaran

Shankarnarayan Bhat

Sanjay Muchini

Arun Balachandar

Devadatta Bhat

A method and apparatus for reducing memory built-in self-test (MBIST) area by optimizing the number of interfaces required for testing a given set of memories is provided. The method begins when memories of a same configuration are grouped together. One memory is then selected from each of the groups. MBIST insertion is then performed for a selected group of memories, and the selected group of memories contains memories of different configurations. Control logic is used to select each group of memories separately. The memory group under test may also be selected using programmable user bits. An apparatus is also provided. The apparatus includes: a controller, at least one memory interface in communication with the controller, at least one control logic cloud in communication with the at least one memory interface; and at least one bit bus.

Method and apparatus for multiple memory shared collar architecture

Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.

Method and apparatus for optimized memory test status detection and debug

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Bengaluru, India

Abhinav Kothiala