Nxp B.v.

Nxp Usa, Inc.

Abhinav Gaur

Neha Bagri

Nipun Mahajan

A system-on-chip includes a memory, an error injection controller, an injection logic circuit, and an error detection circuit. The error injection controller is configured to generate and transmit error data, and at least one of read and write access requests associated with the memory to the injection logic circuit. The injection logic circuit is configured to access the memory based on at least one of the read and write access requests to execute at least one of read and write operations. The injection logic circuit is further configured to inject an error in at least one of first data and second data to generate at least one of erroneous first data and erroneous second data, respectively. The error detection circuit is configured to detect an error in at least one of the erroneous first data and the erroneous second data to generate an error signal.

System and method for error injection in system-on-chip

An error management system can include register sets associated with an error reaction. The test errors are injected in functional signals based on activation of multiple bits in one of the register sets. When the functional signals with the injected test errors are received by the error management system, multiple bits in the other register set are activated. The error management system generates an activated indication signal when a number of the activated bits in one register set matches a number of activated bits in the other register set. When the indication signal is activated, the error management system generates a reaction signal indicative of the error reaction. Thus, the error management system generates a single reaction signal in response to the injected test errors requiring the same reaction.

Growing community of inventors

Agra, India

Abhinav Gaur