Intel Corporation

Abhimanyu Kolla

Kersi H Vakil

Arnaud J Forestier

Jerry G Jex

Jed D Griffin

Adarsh Panikkar

Daniel S Klowden

S Reji Kumar

Wayne C Ashby

Jed c/o Intel Corporation Griffin

Kersi Vakil

In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Transmitters providing cycle encoded signals

Some embodiments include a transmitter having a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Receivers for cycle encoded signals

A method is described that involves loading X bits at a time into a shift register and shifting groups of older, loaded X bits up in the shift register with each new group of loaded X bits. Each group of X bits has been received from a serial data stream. The method further involves identifying an alignment key within the shift register and presenting aligned data from the serial data stream by rotating selection of a first group of Y contiguous bits from the shift register and a second group of Y contiguous bits from the shift register after the identifying. Y is greater than X.

Non-integer word size translation through rotation of different buffer alignment channels

In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.

Dual clock domain deskew circuit

Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.

Training pattern based de-skew mechanism and frame alignment

A signaling apparatus and system may include a data transmitter capable of sending strobe and one or more data streams having edges displaced by time periods corresponding to coded values. Auto-negotiation to compensate for less expensive interconnections may be accomplished using various embodiments of the invention. The data transmitter may be coupled to a medium and a data receiver. An article, including a machine-accessible medium, may contain data capable of causing a machine to carry out a communication method, including transmitting strobe and data streams having edges displaced by time periods corresponding to coded values. A coded information signal may comprise one or more edges displaced in time from various strobe signal edges, the displacement corresponding to coded values.

Adaptive throughput pulse width modulation communication scheme

According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.

Interpolator testing system

According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.

Interpolator linearity testing system

Point-to-point AC impedance compensation calculates and matches AC impedance for integrated circuit input and output buffers, taking into consideration impedances of printed circuit boards, connectors, cards, cables, and/or other interfaces on a computer bus, upon computer system power-up or on demand during operation using no additional package pins or traces in the printed circuit board, connector, card, or cable.

Growing community of inventors

Tacoma, WA, United States of America

Abhimanyu Kolla