Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Microsoft Technology Licensing, LLC

Abhilash Ravi Kashyap

Dale Charles Main

Niles Yang

Deepak Raghu

Rohit Sehgal

Henry Chin

Gautam Ashok Dusija

Pitamber Shukla

Monish Shantilal Shah

Joanna Lai

Brennan Alexander Watt

Chris Nga Yee Yip

The present disclosure relates to systems, methods, and computer-readable media for virtualizing storage resources on non-volatile memory in a way that enables virtual machines on a computing device to efficiently access computing resources across multiple partitions of multiple non-volatile memory devices. For example, systems disclosed herein facilitate establishing a binding (e.g., a physical function, such as a single root input/output virtualization (SR-IOV) or a multi-physical function (MPF)) between the virtual machine(s) and solid state drive (SSD) devices. The systems disclosed herein further involve using a virtual volume manager on an operating system of the virtual machine(s) to implement features and functionality of the virtual machine(s) in accordance with configuration data unique to the virtual machine(s).

Virtualizing shared computing resources

In non-limiting examples of the present disclosure, systems, methods and devices for partitioning dies based on spare blocks and workload expectations are provided. Data from non-volatile storage media may be received. The data may comprise information identifying each of a plurality of dies included in the non-volatile storage media and a number of blocks included in each of the plurality of dies. A number of spare blocks included in each of the plurality of dies may be determined. First and second sets of the plurality of dies may be identified, wherein the first set has a higher number of spare blocks than the second set. A first workload may be assigned to the first set of dies, the first workload being classified as write-intensive. A second workload may be assigned to the second set of dies, the second workload being classified as read-intensive.

Adaptive spare block usage in solid state drives

In an on-chip copy process, performed by a storage device, data is copied from a plurality of Single Level Cell (SLC) blocks of non-volatile three-dimensional memory (e.g., 3D flash memory) in a respective memory die to a Multilevel Cell (MLC) block of the same memory die. A copy of source data from a respective SLC block is interleaved with a copy of source data from one or more other SLC blocks in the memory die to produce interleaved source data. Each source data copy that is interleaved is rotated by an offset assigned to the respective SLC block from which the source data is copied, and each respective SLC block in the plurality of SLC blocks is assigned a distinct offset. Each distinct set of the interleaved source data is written to a distinct respective MLC page of the MLC block.

On-chip copy with data folding in three-dimensional non-volatile memory array

A data storage device includes a solid-state non-volatile memory including a plurality of memory cells and a controller. The controller is configured to reduce a read disturb effect of at least a portion of the solid-state non-volatile memory at least in part by receiving or accessing data to be written to the solid-state non-volatile memory, encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a higher voltage level than the second programming state, and writing the encoded data to the solid-state non-volatile memory.

Read disturb compensation using weighted programming patterns

Technology is described herein for operating non-volatile storage. In one embodiment, the memory system tracks which adjustments to default values for hard bit read reference voltages are most frequently successful to decode data in non-volatile memory cells. In response to a process that uses only hard bits failing to successfully decode data in a group of the non-volatile memory cells, the memory system attempts to decode the data in the group of non-volatile memory cells using dynamic hard bit read reference voltages and dynamic soft bit read reference voltages that correspond to only a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages. By only using a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages time and power is saved.

Adaptive hard and soft bit decoding

In a non-volatile memories formed according to a NAND type of architecture, one or more of the end word lines on the source end, drain end, or both are set aside as dummy word lines that are not used to store user data. In addition to the host data, a memory system typically also stores metadata, or information about the user data, how it is stored and the memory system itself. Techniques are presented for using the dummy word lines of the memory blocks to hold this metadata. This arrangement allows for the metadata of a memory block to be known in real time, without reducing the storage capacity of the memory system.

Use of dummy word lines for metadata storage

A data storage device includes a solid-state memory including memory cells and a controller configured to implement a data protection programming scheme by programming a first subset of the cells to a first voltage state using a first target voltage, programs a second subset to a second voltage state using a second target voltage higher than the first target voltage, programs a third subset to a third voltage state using a third target voltage higher than the second target voltage, and programs a fourth subset to a fourth voltage state using a fourth target voltage higher than the third target voltage. A difference in voltage between the fourth target voltage and the third target voltage may be greater or less than a difference in voltage between the third target voltage and the second target voltage and/or a difference in voltage between the second target voltage and the first target voltage.

Protection against state transition errors in solid-state data storage systems

Systems and methods are disclosed for programming data in non-volatile memory arrays. A data storage device includes a solid-state non-volatile memory including a plurality of memory cells and a controller configured to improve data retention or reduce read disturb of at least a portion of the solid-state non-volatile memory at least in part by receiving data to be written to the solid-state non-volatile memory. The controller is further configured to, when a data retention programming mode is set, encode the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a lower voltage level than the second programming state, and write the encoded data to the solid-state non-volatile memory. When a read disturb programming mode is set, the first programming state is associated with a higher voltage level than the second programming state.

Weighted programming patterns in solid-state data storage systems

A data storage device includes a solid-state memory including memory cells and a controller configured to perform a first programming scheme that programs a first subset of the cells to a first voltage state using a first target voltage, programs a second subset to a second voltage state using a second target voltage higher than the first target voltage, programs a third subset to a third voltage state using a third target voltage higher than the second target voltage, and programs a fourth subset to a fourth voltage state using a fourth target voltage higher than the third target voltage. A difference in voltage between the fourth target voltage and the third target voltage may be greater or less than a difference in voltage between the third target voltage and the second target voltage and/or a difference in voltage between the second target voltage and the first target voltage.

Data retention charge loss and read disturb compensation in solid-state data storage systems

One or more word lines in a Multi Level Cell (MLC) block are identified as being at high risk of read disturb errors and data is selectively copied from such high risk word lines to a location outside the MLC block where the copy is maintained. Subsequent read requests for the data may be directed to the copy of the data outside the MLC block.

Growing community of inventors

San Jose, CA, United States of America

Abhilash Ravi Kashyap