Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Abhijith Prakash

Xiang Yang

Anubhav Khandelwal

Jiahui Yuan

Deepanshu Dutta

Huai-Yuan Tseng

Dengtao Zhao

Yu-Chung Lien

Wei Zhao

Jiacen Guo

Parth Amin

Shubhajit Mukherjee

Masaaki Higashitani

Henry Chin

Shinsuke Yada

Muhammad Masuduzzaman

Anirudh Amarnath

Sujjatul Islam

Kazuki Isozumi

Keyur Payak

Dong-Il Moon

Vishwanath Basavaegowda Shanthakumar

Kyeongran Yoo

Aravind Suresh

A memory apparatus includes memory cells each connected to word lines and configured to store a threshold voltage corresponding to data states. The memory apparatus also includes a control means configured to apply at least one read voltage associated with one of the data states to ones of the word lines connected to the memory cells being read in one read operation. The control means is also configured to adjust a voltage applied to the ones of the word lines during at least one of an end of the one read operation or a beginning of a subsequent read operation of the memory cells based on at least one of the subsequent read operation following the one read operation within a predetermined time or a control gate ready voltage of the ones of the word lines targeted following the one read operation.

Methods to improve current consumption and read time in successive reads

The memory device includes a chip with at least one voltage pump and a plurality of planes. The planes have arrays of memory cells that can be programmed and erased. At least some of the planes are at different distances from the at least one voltage pump. The memory device further includes control circuitry that is configured to program and erase the memory cells. The control circuitry is further configured to supply at least one voltage to a selected plane of the plurality of planes during a programming operation or an erase pulse and adjust the at least one voltage that is supplied to the selected plane by a parameter that is determined based on a distance between the selected plane and the at least one voltage pump.

Plane and block location dependent voltage biases in NAND memory

The memory device an array of memory cells arranged in a word lines and a one common source line (CELSRC) driver. Control circuitry is configured to program the memory cells of a selected word line in a plurality of program loops. During the program loops, the control circuitry sets a voltage of the CELSRC driver to approximately zero Volts, applies a verify voltage to the selected word line, applies a pass voltage to unselected word lines, and applies a bit line voltage to a bit line that is coupled to a memory cell to be sensed. During at least one early program loop for a given data state, the control circuitry increases the bit line voltage or increases the pass voltage. The control circuitry is further configured to reduce the bit line voltage or the pass voltage for the verify operations in at least one subsequent program loop.

Loop dependent bit line and read biases in a memory device

A memory apparatus includes memory cells and a control means configured to adjust at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells in response to determining one of the word lines connected to the memory cells being programmed is susceptible to over-programming. The control means programs non-checkpoint ones of the memory cells associated with a checkpoint state to a verify low voltage for the checkpoint state and programs the non-checkpoint ones of the memory cells to respective non-checkpoint states associated with the checkpoint state by applying the blind program pulses to each non-checkpoint one of the memory cells without verifying whether the non-checkpoint ones of the memory cells have reached their respective non-checkpoint states while applying the bit line voltages to the bit lines associated therewith.

Variable foggy verify levels for selected checkpoint states for non-volatile memory apparatuses

The memory device includes a quick pass write (QPW) voltage source and a transistor that can control the supply of a first QPW bias voltage to a plurality of bit lines. Control circuitry programs the memory cells of a selected word line in a plurality of program loops. For each memory cell in the selected word line, the control circuitry determines if the memory cell is within either a first or a second QPW zone. If the memory cell is in the second QPW zone, the control circuitry connects the QPW voltage source to the bit line that is in communication with that memory cell to supply the first QPW bias voltage to the bit line. In response to a determination that the memory cell is in the first QPW zone, the control circuitry controls the transistor to supply an average second QPW bias voltage to the bit line.

Generation of quick pass write biases in a memory device

A memory apparatus includes memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to identify ones of the plurality of word lines as slow word lines. The control means is also configured to ramp at least one program pulse applied to the slow word lines to a program kick voltage higher in magnitude than a program voltage for a program kick period of time during at least one program loop of a program operation.

Real time ramp rate adjustment for better performance and current consumption tradeoff

A memory apparatus and method of operation are provided. The apparatus includes source-side and drain-side select gate transistors for coupling respectively to the source-side and drain-side of memory holes of memory cells. During the read operation, the control means ramps the word lines to a read pass voltage. The control means is configured to delay ramping the voltage applied to the source-side select gate transistors to a select gate voltage until a predetermined time after the selected ones of the word lines and the unselected ones of the word lines ramp to the read pass voltage. The control means is also configured to delay ramping the voltage applied to the drain-side select gate transistors to a select gate voltage until a different predetermined time after the selected ones of the word lines and the unselected ones of the word lines ramp to the read pass voltage.

Delayed select gate ramp-up for peak read current consumption reduction for non-volatile memory apparatus

Technology is disclosed herein for detecting evolved bad blocks in three-dimensional NAND. The test may include a drain side erase that includes applying an erase voltage from the bit lines and a source side erase that includes applying an erase voltage from the source line(s). If the source side erase performed worse than the drain side erase this may indicate a defect near the source side of the block. For example, the source side erase may fail but the drain side erase may pass. As another example the source side erase may take at least a pre-determined number of additional erase pulses to pass than the drain side erase. If the block is found as having a defect the entire block could be marked bad or the defective region could be identified such that the defective region is no longer used.

Evolving bad block detection in non-volatile memory

Memory die management based on biasing voltages. Some memory dies are formed of memory holes having a semi-circular shape. This semi-circular shape results in a decrease in biasing voltage compared to memory holes having a circular shape. Systems and methods described herein organize memory dies into memory die groups according to their biasing voltages. During operation, data is relocated between the memory die groups based on how often the data is read. Data may be scrambled within their respective memory die groups to maintain appropriate storage space.

Memory die management

The memory device includes a memory block with an array of memory cells arranged word lines. The memory device also includes control circuitry that is configured to program final data into a selected word line in a multi-pass programming operation that includes a first pass and a second pass. In the first pass, the control circuitry is configured to program the memory cells of the selected word line to foggy data and program parity data in the memory device. The parity data includes three possible data states. Prior to the second pass, the control circuitry is configured to read the foggy data and the parity data and reconstruct the final data from the foggy data and the parity data. In the second pass, the control circuitry is configured to program the memory cells of the selected word line from the foggy data to the final data.

Multi-stage programming techniques with three states per memory cell parity

A memory device includes a memory block including a plurality of sub-blocks each including a plurality of memory cells and control circuitry configured to perform single-side erase operations on the memory block in a sub-block mode in which a selected sub-block of the plurality of sub-blocks in the memory block is erased while unselected sub-blocks of the plurality of sub-blocks in the memory block are not erased and selectively perform data scrubbing and relocation operations on the plurality of sub-blocks of the memory block. To perform a data scrubbing and relocation operation, the control circuitry is configured to determine whether to perform the data scrubbing and relocation operation on a first sub-block based on a position of the first sub-block relative to an erase side of the memory block and selectively perform the data scrubbing and relocation operation on the first sub-block in response to the determination.

Single block mode block handling for single-side GIDL erase

The memory device includes a memory block with memory cells arranged in word lines and control circuitry that is configured to program the memory cells in a selected word line to respective programmed data states in program loops, which each include verify operations. The control circuitry is further configured to lock out any of the memory cells in the selected word line memory cell from subsequent program pulses and verify operations in response to that memory cell passing verify for its respective programmed data state. For a selected programmed data state, the control circuitry is further configured to re-verify all of the memory cells in the selected word line that are being programmed to the selected programmed data state and release all memory cells that were locked out but fail re-verify in order to allow any memory cells that mistakenly passed verify to be programmed further.

Intermediate re-verify for achieving tighter threshold voltage distributions in a memory device

A storage device is provided that conditionally performs read refresh in blocks having higher P/E cycles or older programming times, while refraining from performing read refreshes in blocks having lower P/E cycles or recent programming times. The storage device includes a memory and a controller. The memory includes a block having cells. The controller performs a read refresh on the cells when a number of P/E cycles of the block exceeds an age threshold or after a threshold amount time has elapsed since data was programmed in the block. The controller may also refrain from performing read refreshes on the cells until the number of P/E cycles exceeds the age threshold or until a threshold amount of time has elapsed since the data is programmed. As a result, lower BER may occur due to wider Vt margins, while power and system overhead may be saved.

Data retention-specific refresh read

Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.

Bit line modulation to compensate for cell source variation

A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

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Milpitas, CA, United States of America

Abhijith Prakash