Alliance Semiconductor Corporation

Suvolta, Inc.

Virage Logic Corporation

Dsm Solutions, Inc.

Abhijit Ray

Damodar Reddy Thummalapally

Chaitanya Palusa

Vipin Kumar Tiwari

Manish Bhatia

T Damodar Reddy

A voltage-level translator includes an input node, a differential amplifier, first and second output transistors, and a constant current source. The input node receives an input signal. The differential amplifier produces a voltage swing at an amplifier node based at least in part on a difference between the input signal and a voltage supply. The first output transistor provides a substantially constant current to the output node. The voltage swing produced by the differential amplifier prevents forward biasing of the second output transistor. The constant current source provides a substantially constant current both to the differential amplifier and through the first output transistor. The translator outputs a first voltage in an output voltage range at the output node when the input signal is at a high voltage, and outputs a second voltage in the output voltage range at the output node when the input signal is at a low voltage.

Voltage-level translator

A peak current modeling method and system for modeling peak current demand of an integrated circuit (IC) block such as, e.g., a compilable memory instance. A current demand curve associated with the IC for a particular IC block event is obtained via simulation, for example. A defined time region associated with the particular IC block event is divided into multiple time segments, whereupon at least a first current value and a second current value for each time segment is obtained based on the current demand curve. Thereafter, the current demand curve is approximated, on a segment-by-segment basis, using a select approximate waveform depending on a relationship between the first and second current values.

System and method for peak current modeling for an IC design

An output buffer circuit includes a first output transistor having a source terminal connected to a voltage supply and a drain terminal connected to an output node. The first output transistor is capable of coupling the output node to the voltage supply when the input signal is at a high voltage in the input voltage range. The circuit also includes a second output transistor having a drain terminal connected to the output node and a source terminal connected to ground. The second output transistor is capable of coupling the output node to ground when the input signal is at a low voltage in the input voltage range. The circuit further includes a current-limiting circuit coupled to a gate terminal of the first output transistor and capable of limiting a current flowing through the gate terminal when the first output transistor is turned on. The output node outputs an output signal in an output voltage range, wherein a high voltage of the output voltage range exceeds the high voltage of the input voltage range.

Current-limited output buffer

A level-shifting circuit includes an input node, a first output transistor, a second output transistor, a pull-up transistor, and an output node. The input node receives an input signal. The first output transistor turns on when the input signal is at a first voltage level and couples an output node to a positive supply voltage when turned on. The second output transistor, a bipolar junction transistor (BJT), couples the output node to a negative supply voltage when turned on. The pull-up transistor turns on when the input signal is at a second voltage level and generates a voltage at a base terminal of the second output transistor that turns the second output transistor on. Additionally, the level-shifting circuit generates, at the output node, an output signal with a voltage swing that includes a positive voltage range and a negative voltage range.

Level-shifting circuit with bipolar junction transistor

A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line to a second signal line and include one or more switch junction field effect transistors (JFETs) having a first control gate separated from a second control gate by a channel region.

Switching circuits and methods for programmable logic devices

A delay-locked-loop (DLL) that has increased precision and a wide range of operation is formed by utilizing a chain of delay blocks to add or subtract a discreet amount of delay, and a voltage-controlled delay line (VCDL) to add or subtract a smaller amount of delay. The delay blocks allow the delayed clock signal to get close to the reference clock signal, while the VCDL allows the delayed clock signal to lock onto the reference clock signal.

Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings

The diode drops associated with the output voltage from a conventional charge pump are eliminated in the present invention with a dual-chain charge pump that utilizes the pumped voltages from each charge pump chain to drive the gates of the other charge pump chain. As a result, the voltages on the gates of the transistors are pumped up to a level such that there is no threshold voltage drop across the transistor, and thus, making it behave like an ideal switch.

Bootstrapped charge pump

A flash EPROM device (,) is disclosed. During a programming operation, a primary programming voltage circuit (,) drives I/O lines (,) to a programming voltage (Vp) according to input data values. Secondary programming voltage circuits (,) are located remotely from the primary programming voltage circuit (,) and further drive I/O lines to Vp in response to the voltage levels on the I/O lines. This arrangement reduces the effect on the load line response of the impedance intermediate the primary programming voltage circuit (,) and the secondary programming voltage circuits (,).

Nonvolatile memory array having local program load line repeaters

A flash memory architecture relies on a single, time-shared address bus to enable a read operation to be performed simultaneously with an algorithm operation when the read operation is targeted for a memory cell block that is not currently tagged for an algorithm operation. After a read address has been latched into the array block selected for the read operation, the address bus is 'free' for the remainder of the read operation cycle. During this free time, the address bus can be used for algorithm operations to load the counter address into an active tagged block in the array. Separate global data I/O lines are provided to facilitate simultaneous read and algorithm operations.

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Sunnyvale, CA, United States of America

Abhijit Ray