Rambus Inc.

Flex Logix Technologies, Inc.

Other

Intel Corporation

Abhijit Mukun Abhyankar

Frederick Abbott Ware

Richard Maurice Barth

Paul G Davis

Craig Edward Hampel

Donald C Stark

David Nguyen

James A Gasbarro

Scott C Best

Frank Lambrecht

Kun-Yung Chang

Suresh Rajan

Thomas J Giovannini

David A Secker

Ravindranath T Kollipara

Jared L Zerbe

Ely K Tsern

Cheng C Wang

Andrew V Anderson

William Franklin Stonecypher

Thomas J Holman

Michael Tak-Kei Ching

Andy Peng-Pui Chan

Peter D MacWilliams

Nitish U Natu

Kun Yung Chang

Ming Chu Li

Kambiz Kaviani

Anthony Kozaczuk

Arun Vaidyanath

Donald R Mullen

James A Gasborro

James A Gasbarre

Adrian F Torres

A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

Burst-tolerant decision feedback equalization

Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

High performance, high capacity memory modules and systems

A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

High capacity memory system with improved command-address and chip-select signaling mode

A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

Drift tracking feedback for communication channels

An integrated circuit comprising (1) an array of logic tiles including a first and a second plurality of logic tiles, wherein each logic tile of the array is configurable to electrically connect with at least one other logic tile, and (2) a clock mesh fabric to provide a mesh clock signal to the first plurality of the logic tiles. Each logic tile of the first plurality includes clock distribution and transmission circuitry including: (1) tile clock generation circuitry configurable to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals of each logic tile of the first plurality of logic tiles, and (2) clock selection circuitry configurable to receive the mesh clock signal and the tile clock signal and responsively output the tile clock to the circuitry which performs operations using or based on the associated tile clock.

Clock architecture, including clock mesh fabric for FPGA, and method of operating same

An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.

FPGA having a virtual array of logic tiles, and method of configuring and operating same

An integrated circuit comprising (i) an array of logic tiles wherein each logic tile is configurable to connect with at least one adjacent logic tile and (ii) a clock mesh fabric including a clock mesh to provide a mesh clock signal to each of the logic tiles of the array of logic tiles. In one embodiment, each logic tile of the array of logic tiles includes (1) distribution and transmission circuitry configurable to provide an associated tile clock to circuitry which performs operations using or based on the associated tile clock, wherein the distribution and transmission circuitry includes circuitry to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals generated by the generation circuitry of each tile, and (2) selection circuitry to responsively output the associated tile clock which corresponds to the mesh clock signal or the tile clock signal.

Clock architecture, including clock mesh fabric, for FPGA, and method of operating same

Growing community of inventors

Sunnyvale, CA, United States of America

Abhijit Mukun Abhyankar