Intel Corporation

Abhijit Davare

Srikanth T Srinivasan

Jonathan D Pearce

Jeffrey J Cook

David B Sheffield

Anton Alexandrovich Sorokin

Andrey Ayupov

Desmond A Kirkpatrick

Eriko Nurvitadhi

Deborah T Marr

Asit K Mishra

Steven Burns

Rajesh M Sankaran

Ren Wang

David W Grawrock

Jr-Shian Tsai

Sameh Gobriel

Narayan Ranganathan

Edwin Verplanke

Bruce Querbach

Nilesh K Jain

Brinda Ganesh

Tieyu Zheng

Keshavan K Tiruvallur

Yipeng Wang

Mark B Trobough

Somnath Paul

Chinna B Prudvi

Vui Yong Liew

Hermann Gartler

Ashok N Kabadi

Keith A Drescher

Samie B Samaan

Jay Joseph Nejedlo

Mukesh Kataria

Mrittika Ganguli

Lyle E Cool

Russell J Wunderlich

James J Grealish

Sriram Kabisthalam Muthukumar

Brian Meyer

Priya Autee

Abhirupa Layek

Priyadarsan Patra

Debbie Marr

William Penner

Rahima K Mohammed

Ridvan A Sahan

Kapila B Udawatta

Wee Hoo Cheah

Yuen Tat Lee

John L Baudrexl

Arun R Ramadorai

Loren James McConnell

Christian E Iovin

Kip C Killpack

Kyle Markley

Suvadeep Banerjee

Shaman Narayana

Travis K Goff

Nalini Murari

Evan J Halprin

Jiun Long Foo

Selvakumar Raja Gopal

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Jaykant B Timbadiya

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Rishiraj A Bheda

Sanjay S Salem

David C Florey

Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

Hardware offload circuitry

An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule matrix operations responsive to a matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, wherein a lane comprises an arithmetic logic unit to multiply a block of a first matrix with a block of a second matrix to generate a product and to accumulate the product with a block of a third matrix, and wherein the matrix blocks are to be stored in registers within the lane; and broadcast circuitry to broadcast one or more invariant matrix blocks to at least one of different registers within the lane and different registers across different lanes.

Apparatus and method for adaptable and efficient lane-wise tensor processing

In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.

Gather-scatter cache architecture having plurality of tag and data banks and arbiter for single program multiple data (SPMD) processor

An apparatus and method for data parallel single program multiple data (SPMD) execution. For example, one embodiment of a processor comprises: instruction fetch circuitry to fetch instructions of one or more primary threads; a decoder to decode the instructions to generate uops; a data parallel cluster (DPC) to execute microthreads comprising a subset of the uops, the DPC further comprising: a plurality of execution lanes to perform parallel execution of the microthreads; an instruction decode queue (IDQ) to store the uops prior to execution; and a scheduler to evaluate the microthreads based on associated variables including instruction pointer (IP) values, the scheduler to gang microthreads into fragments for parallel execution on the execution lanes based on the evaluation.

Architecture and method for data parallel single program multiple data (SPMD) execution

An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule a plurality of matrix operations responsive to a tensor matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, each lane comprising: first, second, and third tile registers to store blocks of a first matrix (A), second matrix (B), and third matrix (C), respectively; at least one tensor arithmetic logic unit (TALU) to multiply a block of elements of the first matrix with a block of elements of the second matrix to generate a product and to accumulate the product with a block of elements of the third matrix, wherein each lane is to multiply one or more different blocks of the first and second matrix and to accumulate the resulting one or more products with one or more different blocks of the third matrix; and broadcast circuitry to broadcast one or more invariant matrix blocks to different tile registers within a lane and/or different tile registers across different lanes.

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

Growing community of inventors

Hillsboro, OR, United States of America

Abhijit Davare