Georgia Tech Research Corporation

Other

Samsung Electronics Co., Ltd.

University of Florida Research Foundation, Incorporated

Nec Usa, Inc.

Ardext Technologies, Inc.

Abhijit Chatterjee

Shreyas Sen

Sasikumar Cherubal

Shyam Kumar Devarakond

Soumendu Bhattacharya

Vishwanath Natarajan

Sankar Nair

William Richard Eisenstadt

Pramodchandran Variyam

Sung Yeol Kim

Rabindra K Roy

Ho Sun Yoo

Douglas Leonard Goodman

Adit D Singh

Alfred Gomes

Jacob A Abraham

Hyun Woo Choi

Rajarajan Senguttuvan

Dong Hoon Han

Sabyasachi Deyati

Selim Sermet Akbay

Maryam Ashouei

Donghoon Han

Barry John Muldrey

Shalabh Goyal

Achintya Halder

Nicholas Tzou

Ram Voorakaranam

Dave Majernik

Xian Wang

Sudip Chakrabarti

Aritra Banerjee

Thomas Moon

Ramakrishna Voorakaranam

An authenticating circuit includes a first and second challenge vector input, a first and second highly variable process-dependent circuit and a logic circuit. The first highly variable process-dependent circuit receives a first vector from the first challenge vector input and generates a first output that is a function of the first vector and at least one process-dependent feature of a component of the first highly variable process-dependent circuit. The second highly variable process-dependent circuit receives a second vector from the second challenge vector input and generates a second output that is a function of the second vector and at least one process-dependent feature of a component of the second highly variable process-dependent circuit. The logic circuit generates a response output that is a function of the first output and the second output. The function operates so that the response output is independent of environmental conditions of the authenticating circuit.

Analog push pull amplifier-based physically unclonable function for hardware security

An amplifier having orthogonal tuning elements is provided. In one embodiment, an amplifier comprises an input amplifier stage having a first tuning element used to control a first performance criteria of the amplifier; an output amplifier stage operatively coupled to the first amplifier stage; a bias circuit operatively coupled to the second amplifier stage and having a second tuning element used to control a second performance criteria of the amplifier; and wherein the first tuning element operates substantially independent of the second tuning element.

Amplifier having orthogonal tuning elements

An exemplary embodiment of the present invention provides an adaptive power amplifier comprising a transistor, a resistive load, and a tuning circuit. The transistor has a drain, a source, and a gate. The resistive load can be electrically coupled to the drain. The tuning circuit can be electrically coupled to the drain in parallel with the transistor. The tuning circuit can comprise an inductor and a capacitive element. The inductor and capacitive element can be in series connection.

Adaptive power amplifier and methods of making same

The various embodiments of the present disclosure relate generally to power-conscious self-healing transceiver systems and methods. An embodiment of the present invention provides a method of power-consciously self-healing a transceiver system. The method comprises providing a transceiver device having a plurality of tuning elements configured to control a plurality of specifications of the device, determining initial values for the plurality of tuning elements, and performing a hardware-iterative gradient search to obtain values for each tuning element such that the plurality of specifications are within a tolerated range.

Power conscious self-healing transceiver systems and methods

An apparatus for measuring a high speed signal may comprise a plurality of Analog-Digital converters (AD converter) that are arranged in parallel to each other to sample an input signal at different frequencies; a plurality of frequency synthesizers configured to provide each AD converter with a different sampling frequency; a signal processor configured to receive an output of the plurality of AD converters to reconstruct the input signal; and/or a controller configured to receive and process a trigger signal.

Apparatuses for measuring high speed signals and methods thereof

An exemplary embodiment of the present invention provides a method of measuring I-Q mismatch in a system having a transmitter. The transmitter comprises an in-phase up-converter, a quadrature-phase up-converter, and a power detector. The method of measuring I-Q mismatch comprises measuring an in-phase transmit power at the power detector caused by transmitting an in-phase output signal to the in-phase up-converter, measuring a quadrature-phase transmit power at the power detector caused by transmitting a quadrature-phase output signal to the quadrature-phase up-converter, calculating a transmitter-gain-mismatch as a function of the in-phase transmit power and the quadrature-phase transmit power, measuring an I-Q transmit power at the power detector caused by simultaneously transmitting a gain-mismatch-compensated in-phase output signal to the in-phase up-converter and a gain-mismatch-compensated quadrature-phase output signal to the quadrature-phase up-converter, and calculating a transmitter-phase-mismatch as a function of the I-Q transmit power.

Systems and methods for measuring I-Q mismatch

The presently invention is directed to ways to measure distortion effects while allowing for the possibility of significant reduction in test cost. An exemplary embodiment of the present invention provides a method for amplifier distortion measurement including comparing a first amplitude response of an output signal from a power amplifier to a second amplitude response of a reference input signal to determine a set of Amplitude-to-Amplitude ('AM-AM') distortion values. Additionally, the method for amplifier distortion measurement includes equalizing the first amplitude response of the output signal to match the second amplitude response of the reference input signal based on the set of AM-AM distortion values and creating a difference signal based on a comparison of the equalized output signal to the reference input signal. Furthermore, the method for amplifier distortion measurement includes calculating a set of Amplitude-to-Phase ('AM-PM') distortion values based on a third amplitude response of the difference signal.

Systems and methods for distortion measurement using distortion-to-amplitude transformations

Systems and methods are disclosed for evaluating the length of elongated elements in a sample. The disclosed systems and methods may include using a direct current stimulus to determine a direct current base length region corresponding to at least a portion of the sample. Furthermore, the disclosed systems and methods may include using an alternating current stimulus to determine that the direct current base length region corresponds to a first set of elongated elements and a second set of elongated elements. The first set of elongated elements may have a first base length and the second set of elongated elements may have a second base length. The elongated elements may comprise, for example, chain molecules, deoxyribonucleic acid (DNA), ribonucleic acid (RNA), or proteins. Furthermore, the disclosed systems and methods may include measuring an ion current through a nanopore, the ion current produced by the alternating current stimulus.

Methods and systems for evaluating the length of elongated elements

Various embodiments of self-calibration systems and methods are described. One method embodiment, among others, includes imposing an alternate test to components within the device, responsive to the imposition of the alternate test, providing test responses corresponding to the components, and substantially, simultaneously mapping each of the test responses to corresponding specification values of the components.

Self-calibration systems and methods

The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.

Systems and methods for providing defect-tolerant logic devices

A single test stimulus and a simple test configuration with embedded envelope detectors are used to estimate all the specification values of interest for an RF circuit under test in an integrated circuit chip. Envelope detectors are deployed as sensors inside the circuit under test. Where more than one circuit is in an RF device in the integrated circuit, each RF circuit in the device may have its own envelope detector. A signal having, for example, time-varying envelopes is used as an optimized test stimulus. The test uses the time-varying and low frequency envelope of the test response. The circuit's response under test to the optimized test stimulus has features highly correlated with the specifications of interest. The test stimulus is optimized for a set of training circuits, and each training circuit in the set is selected to provide one of a spectrum of test responses to the stimulus.

Production test technique for RF circuits using embedded test sensors

Devices and methods to test high speed analog-to-digital and digital-to-analog signal converters are provided. According to one embodiment, a testing device can comprise an output, a mixer, and an input. The output can provide a signal, and the mixer can receive the signal and provide a test signal to a data converter having a sampling frequency. The test signal can be spectrally impure. The input can sample the data converter output at a frequency less the sampling frequency so that the data converter output is under sampled. According to another embodiment, a first set of data converters are tested to obtain a mapping function that relates dynamic specifications to device signatures. Then a second set of data converters can be tested and based on their device signatures mapped with the mapping function, dynamic specifications for the second set of data converters can be obtained. Other embodiments are also claimed and described.

High speed data converter testing devices, methods, & systems

A bit error rate test on a transceiver is accelerated by adding a phase offset to data phase encoding and decoding in the transceiver and by mapping bit error rate test results from an elevated error rate condition to a normal error rate condition for the transceiver. The elevated error rate is accomplished by adjusting the phase of the phase encoder and decoder with the value of the phase offset so that the encoded data transmission signal is not as robust against noise as it normally would be. Noise in the form of an interference signal is introduced during the transmission, and the bit error rate is measured after the receiver has decoded the signal. The bit error rate (BER) data with an elevated propensity for error is mapped against bit error rate data for normal operations. A mapping function is built to map BER(bit error rate elevated) data&#x2014;data from the elevated error rate condition for data encoding, to BER(normal bit error rate) data&#x2014;data from the normal error rate condition for data encoding. The BERdata is mapped to BERdata using the mapping function so that the BER performance of the transceiver may be measured using far fewer test sequences of digital bits.

Measuring bit error rate of radio frequency transceivers

Systems and methods for digital-based, standards-compatible, testing of analog circuits embedded inside integrated circuits. In this regard, one such system can be broadly described by a test stimulus generator that transmits a binary-level test-stimulus signal into an analog circuit located inside an integrated circuit; a converter that converts an analog output signal from the analog circuit into a digital output signal; a boundary-scan register chain that transmits the digital output signal out of the integrated circuit, and a test equipment that receives the digital output signal using the IEEE 1149.1 boundary-scan standard and analyzes the digital output signal to compute one or more specifications of the analog circuit located inside the integrated circuit.

Systems and methods for testing integrated circuits

A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.

Growing community of inventors

Marietta, GA, United States of America

Abhijit Chatterjee