Synopsys, Inc.

Abhijeet Samudra

Anubhav Sinha

Ramalingam Kolisetti

Ajay Nagarandal

Salvatore Talluto

Brian Archer

Firooz Massoudi

Bala Tarun Nelapatla

Amit Kapatkar

Venkata Raja Ramchandar Koneru

Kranthi Kandula

Jatin Verma

Yongkang Hu

Akshay Kumar Gupta

Saransh Nagaich

Naresh Thakur

Milin Kaushik Raijada

Hemasagar Babu Reddy

Luis M Cruz

A device includes a processing device, a set of local resources coupled to the processing device, a plurality of parent interfaces, and a plurality of child interfaces. Each parent interface and each child interface is configured to couple the processing device to a respective node residing outside of the device when selected. The processing device is to select one parent interface, such that a selection of the one parent interface causes the respective node coupled to the one parent interface to operate as a parent of the processing device. The processing device is to further select one child interface, such that a selection of the one child interface causes the processing device to operate as a parent of the respective node coupled to the one child interface.

Dynamically configurable system-on-chip network

Certain aspects are directed to apparatus and methods for signal integrity monitoring. The method generally includes: receiving a data signal; generating a first set of delayed versions of the data signal via a plurality of delay elements; comparing each of the first set of delayed versions of the data signal with a clock signal; and generating an output signal based on the comparison.

Signal integrity monitoring system

Systems, integrated circuits and methods for synchronizing testing a Device under test (DUT) with an automated test equipment (ATE) is provided. In one example, a method includes transmitting a test packet from an ATE to a first Device Under Test DUT; receiving, at the ATE from the DUT, a result packet; and in response to receiving a Start of Packet (SOP) indicator from the DUT at the ATE, evaluating the first DUT by comparing the result packet to an expected packet associated with the test packet.

Device under test synchronization with automated test equipment check cycle

Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals. Response packets may be sent to the ATE by the circuit in the DUT at regular time intervals, where the response packets may include a portion of the test response data (which may be encoded using an encoding technique), and where the response packets may be sent to ATE over the SERDES connection.

Deterministic data latency in serializer/deserializer-based design for test systems

An integrated circuit (IC) device and a method for communicating test data utilizes test control circuitry, and a test controller. The test controller is coupled with the test control circuitry and decodes packetized test pattern data to identify configuration data for the test controller and test data for the test control circuitry. The test controller further communicates the test data to the test control circuitry, and packetizes resulting data received from the test control circuitry. The resulting data corresponds to errors identified by a test performed based on the test pattern data.

High-speed functional protocol based test and debug

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Santa Clara, CA, United States of America

Abhijeet Samudra