Cadence Design Systems, Inc.

Abhijeet S Kolpekwar

Chandrashekar Lakshminarayanan Chetput

Aaron Mitchell Spratt

William Scott Cranston

Srinivasan Iyengar

Donald John O'Riordan

Timothy Martin O'Leary

Peter Frey

Ramesh S Mayiladuthurai

Prasenjit Biswas

Scott Cranston

Iyengar Srinivasan

Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.

Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language

Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic circuits with specialized power management requirements, such as low power designs. Some approaches provide an improved method and system for providing a highly reliable, usable and scalable solution to allow for designers to use their power information files in a mixed-signal simulation and carry the impact of power intents defined on the digital blocks onto the analog blocks without needing any manual changes to models/designs.

Method and mechanism for verifying and simulating power aware mixed-signal electronic designs

For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.

Analog/digital partitioning of circuit designs for simulation

Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic designs. An improved approach for providing seamless interaction between analog and digital blocks during simulation, even if the digital blocks include complex types or models.

Method and mechanism for performing mixed-signal simulation of electronic designs having complex digital signal types or models

For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.

A system, method, and computer program product is disclosed for utilizing dual-value signals, such as hierarchical dual-value signals, for mixed-signal simulation. Such dual-value signals can hold both analog and digital representations of a signal and use the appropriate representations based on which block (analog or digital) for which there is an interaction.

Method and system for supporting both analog and digital signal traffic on a single hierarchical connection for mixed-signal verification

A method is provided to coerce a wire type net in an integrated circuit design to become a wreal net in the design, comprising: running a wreal coercion process on a computer system including the acts of, identifying a wire type net that is connected to a wreal net in an integrated circuit design; and converting the identified wire type net to a wreal net.

Using real value models in simulation of analog and mixed-signal systems

A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process.

Method and system for re-using digital assertions in a mixed signal design

Connections between digital blocks and other circuit components, such as power supplies and clocks, are verified using a discrete property or object, such as a discrete discipline. A discrete discipline is defined for each value of an operating parameter, such as voltage or clock speed, that is used in a circuit design. Each discrete discipline is propagated throughout respective nets using bottom-up and/or top-down propagation. As a result, each digital net is associated with a power supply value through its corresponding discrete discipline. A determination is made whether two digital nets are connected to each other within the same digital island. If so, a determination is made whether the digital nets are compatible. If they have conflicting discrete disciplines, then they are not compatible and an error report or signal can be generated to identify the incompatibility and its location. Compatibility checks can disregard grounded digital nets. Verifications can be performed for both digital and mixed signal digital/analog designs without running simulations.

Method for verifying connectivity of electrical circuit components

System and method for representing analog connectivity in a design written in a hardware description language are disclosed. The method includes detecting a circuit component that does not have explicit connection path in the design, where the circuit component includes one or more lower-level circuit instances arranged in one or more branches in a hierarchical graph. The method further includes creating one or more instances of the circuit component having at least one additional port than the circuit component, creating one or more ports in the corresponding one or more instances of the circuit component for providing at least an explicit connection path, and representing the design using at least the explicit connection path and the one or more ports of the corresponding one or more instances.

Method and system for representing analog connectivity in hardware description language designs

A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first Verilog-AMS component in accordance with the predetermined set of connection rules, and connecting the first VHDL-AMS component to the first Verilog-AMS component.

Growing community of inventors

Round Rock, TX, United States of America

Abhijeet S Kolpekwar