Sandisk Technologies Inc.

Pandocorp Private Limited

Abhijeet Manohar

Daniel Edward Tuers

Chris Avila

Dana Lee

Nian Niles Yang

Aaron Lee

Yehuda Hahn

Gautam Ashok Dusija

Chris Nga Yee Avila

Jian Feng Chen

Jianmin Huang

Henry Chin

Mrinal Kochar

Narendhiran Chinnaanangur Ravimohan

Nicholas Thomas

Muralitharan Jayaraman

Jonathan Hsu

Vijay Sivasankaran

Deepanshu Dutta

Steven Theodore Sprouse

Yoav Weinberg

Hua-Ling Cynthia Hsu

Yichao Huang

Yosief Ataklti

Vivek Shivhare

Anne Pao-Ling Koh

Milton Lourenco Barrocas

Cynthia Hua-Ling Hsu

Venkata Krishna Nadh Dhulipala

Rishi Gautam Mukhopadhyay

Rajesh Kumar Neermarga

Idan Alrod

Sergey Anatolievich Gorobets

Menahem Lasser

Alan David Bennett

Mark Murin

Tien-Chien Kuo

Anubhav Khandelwal

Sahil Sharma

Mark Shlick

Cynthia Hsu

Chun Sum Yeung

Gadi Vishne

Gary Lin

Vimal Kumar Jain

Jong Hak Yuh

Mikhail Palityka

Girish Desai

Vered Kelner

Nagi Reddy Chodem

Yong Huang

Noga Deshe

Sathyanarayanan Subramanian

Ivan Baran

Victor Avila

Derek McAuley

Siddhant Malhotra

Raja Alwar Gopinath

Nurit Appel

Sujeeth Joseph

Thomas Ta

Krishanu Seal

A method () and system () for optimizing delivery of consignments is disclosed. Real-order data for delivering a consignment including a plurality of packages is received. The real-order data includes package related information and vehicle related information, which are pre-processed to generate a plurality of inputs. A machine learning model () trained using DRL is selected to optimize an objective function of minimizing an overall cost of consignment delivery by optimizing a number of vehicles selected for consignment delivery and optimizing a number of consignees and a number of drop locations serviced by each selected vehicle. The plurality of inputs is provided to the machine learning model () to predict a sequence of loading actions in relation to loading of the plurality of packages in the vehicles. A loading plan () is generated based on the sequence of loading actions. The loading plan () optimizes the delivery of the plurality of packages associated with the consignment.

Method and system for optimizing delivery of consignments

A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.

Dynamic management of programming states to improve endurance

A memory system may use adaptive trimming to control throughput and traffic from the host to/from the memory. The trimming parameters of memory may be adaptively changed based on the data rate from the host. The programming speed may be slowed in order to reduce wear and improve endurance. In particular, the data rate for the transfer of data from a data buffer to the memory (e.g. NAND flash) may be matched to the host data rate. This programming speed reduction may be triggered upon prediction of idle times in the host bus.

Inherent adaptive trimming

A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Biasing schemes for storage of bits in unreliable storage locations

A data storage device includes an encoder and a memory that includes multiple storage elements. The encoder is configured to receive input data and to map at least one input group of bits of the input data to generate output data including at least one output group of bits. Each input group of bits of the at least one input group of bits and each output group of bits of the at least one output group of bits has the same number of bits. Each storage element of the multiple storage elements is configured to be programmed to a voltage state corresponding to an output group of bits of the at least one group of bits associated with the storage element.

Data coding

In a multi-plane non-volatile memory, good blocks of different planes are linked for parallel operation for storing long host writes. Where bad blocks in one or more planes result in unlinked blocks, the unlinked blocks are configured for individual operation to store short host writes and/or memory system management data. Unlinked blocks may be configured as Single Level Cell (SLC) blocks while linked blocks may be configured as SLC blocks or Multi Level Cell (MLC) blocks.

Adaptive block allocation in nonvolatile memory

A non-volatile memory system may include a write task queue that queues write commands and a garbage collection module that analyzes information about pending write commands in the write task queue in order to perform garbage collection. Based on its analysis of the write task queue, the garbage collection module performs discouraging actions to discourage itself from selecting certain blocks in a candidate list to be source blocks for garbage collection. In addition or alternatively, the garbage collection module performs encouraging actions to encourage itself to select blocks storing current valid data associated with a write command as source blocks for garbage collection. Write amplification may be reduced as a result of the discouraging and encouraging actions.

Garbage collection based on queued and/or selected write commands

A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are provided.

Memory system and method for improving write performance in a multi-die environment

A cluster association recognition system and related method are described. The system may identify sequences of data clusters in compilations of cluster journals. The system may generate the compilations by populating the cluster journals with cluster identifications associated with host addresses identified in host read requests. Upon receipt of future read requests, the cluster sequences may be used to identify data sets that are associated with a cluster sequence in order to identify further data sets that a host is likely to request.

Self-describing cluster association

A memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment are provided. In one embodiment, a memory die is provided comprising a memory array, an interface, at least one register, and circuitry. The circuitry is configured to receive, via the interface, a pause command from a controller in communication with the memory die; and in response to receiving the pause command: pause a data transfer between the memory die and the controller; and while the data transfer is paused and until a resume command is received, maintain state(s) of the at least one register irrespective of inputs received via the interface that would otherwise change the state(s) of the at least one register. Other embodiments are provided.

Memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment

A storage device utilizing read look ahead (RLA) may utilize auxiliary or spare latches as a RLA cache for storing pre-fetch data. The RLA may predict the next commands and do a speculative read to the flash using the latches for RLA storage. The auxiliary/spare latches may be present on a plane or die of non-volatile memory and may be different from the transfer data latch (XDL) that transfers data from the memory and the host. When the XDL is backed up, sense commands may still be performed and the data is stored in the auxiliary latches before being transferred with the XDL.

Preserving read look ahead data in auxiliary latches

A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.

Memory system and method for reducing read disturb errors

A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an error correction coding (ECC) decoder. The non-volatile memory is configured to sense hard bit data and soft bit data corresponding to multiple ECC codewords from a word line of the non-volatile memory and to sense soft bit data for the multiple ECC codewords. The soft bit data includes sub codes for each of the multiple ECC codewords. The non-volatile memory is configured to send less than all of the sensed soft bit sub codes to the ECC decoder.

Partial soft bit read

Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.

Techniques for reducing read disturb in partially written blocks of non-volatile memory

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Bengaluru, India

Abhijeet Manohar