Sandisk Technologies Inc.

Abhijeet Bhalerao

Mrinal Kochar

Aaron Lee

Mikhail Palityka

Dennis S Ea

Yew Yin Ng

Ivan Baran

Piyush Girish Sagdeo

Preeti Yadav

Derek McAuley

Barys Sarana

Frederick Fernandez

Namita Joshi

A system and method for operating a memory system includes receiving a first user data, writing the first user data to a first buffer, writing the first user data from the first buffer to a first selected memory location, writing the first user data from the first buffer into a second buffer when the first user data was successfully written to the first selected memory location. Data is retrieved from the first selected memory location and written into the first buffer. Data in the first buffer can be matched to the user data in the second buffer to confirm a successful storage of the first user data in the memory system. A previously stored user data can be retrieved from a third selected memory location and written into a third buffer when the previously stored user data was stored in the memory system before the first user data.

System, method and apparatus for preventing data loss due to memory defects using latches

Data that is initially stored in Single Level Cell (SLC) blocks is subsequently copied (folded) to a Multi Level Cell (MLC) block where the data is stored in MLC format, the data copied in a minimum unit of a fold-set, the MLC block including a plurality of separately-selectable sets of NAND strings, data of an individual fold-set copied exclusively to two or more word lines of an individual separately-selectable set of NAND strings in the MLC block.

Data folding in 3D nonvolatile memory

Systems and methods for partial bad block reuse may be provided. Data may be copied from a block of a first memory to a block of a second memory. A post write read error may be detected in a first portion the data copied to the block of the second memory without detection of a post write read error in a second portion of the data copied to the block of the second memory. The block of the second memory may be determined to be a partial bad block usable for storage in response to detection of the post write read error in the first portion of the data but not in the second portion of the data.

Partial bad block detection and re-use using EPWR for block based architectures

Partially-bad blocks are identified in a 3-D block-erasable nonvolatile memory, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings. Operable sets of NAND strings within two or more partially-bad blocks are identified and are mapped to form one or more virtual blocks that are individually assigned virtual block addresses. The virtual block address are maintained in a list and used to access the virtual blocks.

Partially-bad block operation in 3-D nonvolatile memory

Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an initial word line of the memory block or a last word line of the memory block dependent on the write direction. The controller is further configured to erase the memory unit and, in response to erasing the memory unit, modify the identifier to change the write direction for a subsequent write of data to the memory block.

Non-volatile memory systems with multi-write direction memory units

Methods are provided for programming multi-level non-volatile memory cells, the multi-level non-volatile memory cells accessible by a plurality of word lines. The methods include using a four-pass programming technique to program a block of the multi-level non-volatile memory cells, detecting a power cycle before completing programming of the block of the multi-level non-volatile memory cells, and upon power-up initialization, resuming programming on the block of the multi-level non-volatile memory cells.

Initialization techniques for multi-level memory cells using multi-pass programming

A nonvolatile memory die is tested to determine certain parameters such as read time, which are then recorded in the nonvolatile memory die. After the die is incorporated into a memory system, and firmware is downloaded, the nonvolatile memory system uses the recorded parameters to determine how to configure the memory system for operation within specified limits, such as determining how much delay to apply to read operations.

Memory system performance configuration

A system and method for adaptive enhanced post write reads (EPWRs) is provided. An error rate of a block of solid state memory may be determined. Foldings may be performed more times between two consecutive enhanced post write reads on the block when the determined error rate of the block is a lower value than when the determined error rate is a higher value. The foldings may be performed by folding data into the block of the solid state memory.

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San Jose, CA, United States of America

Abhijeet Bhalerao