Nvidia Corporation

Abhijat Ranade

Alan Menezes

Thomas Melvin Ogletree

Shounak Kamalapurkar

Roger L Allen

Timothy J McDonald

Pranav Vaidya

Gregory Paul Smith

Yogesh Kulkarni

Gongyu Zhou

Tom Ogletree

Jin Ouyang

Various embodiments include a system for generating performance monitoring data in a computing system. The system includes a unit level counter with a set of counters, where each counter increments during each clock cycle in which a corresponding electronic signal is at a first state, such as a high or low logic level state. Periodically, the unit level counter transmits the counter values to a corresponding counter collection unit. The counter collection unit includes a set of counters that aggregates the values of the counters in multiple unit level counters. Based on certain trigger conditions, the counter collection unit transmits records to a reduction channel. The reduction channel includes a set of counters that aggregates the values of the counters in multiple counter collection units. Each virtual machine executing on the system can access a different corresponding reduction channel, providing secure performance metric data for each virtual machine.

Generating power efficient secure multiclient performance monitoring data

A processing unit can include a performance monitor for monitoring the performance of the processing unit and associated sub-units. The performance monitor can include a state machine. The state machine can be implemented via state machine data entries stored in a memory associated with the performance monitor. A state machine data entry includes information indicating a state transition condition and output signals. The state transition condition includes a current state and input signals required to meet the condition. The output signals include a next state, one or more counter actions, and one or more triggers. The performance monitor implements logic circuits that determine, based on input signals and the state machine data entries, the next state to transition and associated output signals. The state machine data entries can be written and re-written by a user.

Programmable state machine for a hardware performance monitor

Performance monitors are placed on computational units in different clock domains of an integrated circuit. A central dispatcher generates trigger signals to the performance monitors to cause the performance monitors to respond to the trigger signals with packets reporting local performance counts for the associated computational units. The data in the packets are correlated into a single clock domain. By applying a trigger and reporting system, the disclosed approach can synchronize the performance metrics of the various computational units in the different clock domains without having to route a complex global clock reference signal to all of the performance monitors.

Efficient performance monitoring of integrated circuit(s) having distributed clocks

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Austin, TX, United States of America

Abhijat Ranade