Freescale Semiconductor,inc.

Freescale Semiconductors Inc.

Abhijat Goyal

James D Whitfield

Chai Ean Gill

Rouying Zhan

Chai Ean E Gill

An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb'. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb&#x2032;. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vtis low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vtrises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

Multi-voltage electrostatic discharge protection

An electrostatic discharge (ESD) clamp (), coupled across input-output (I/O) () and common (GND) () terminals of a protected semiconductor SC device or IC (), comprises, an ESD transistor (ESDT) () with source-drain () coupled between the GND () and I/O (), a first resistor () coupled between gate () and source () and a second resistor () coupled between ESDT body () and source (). Paralleling the resistors () are control transistors () with gates () coupled to one or more bias supplies Vb, Vb'. The main power rail (Vdd) of the device or IC () is a convenient source for Vb, Vb&#x2032;. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vtis low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vtrises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT () during normal operation is much reduced.

An electrostatic discharge (ESD) protection device (), coupled across input-output (I/O) () and common () terminals of a core circuit () that it is intended to protect from ESD events, comprises, multiple serially coupled ESD clamp stages (), each stage () comprising an interior node () and first () and second terminal () nodes wherein the first terminal node () of the first clamp stage () is coupled to the common terminal () and the second terminal node () of the last clamp stages () is coupled to the I/O terminals (). A resistance-capacitance ladder () is provided in parallel with some of the clamp stages (), with a resistance (R, R, Retc.) coupled to each of the nodes (()) of one of the ESD clamp stages () by first terminals thereof and capacitors (C, C, etc.) are coupled between second terminals of the resistances (R, R, Retc.). The clamp stages () are desirably bi-directional and a diode (D) may bridge one or more of the clamp stages (e.g.,) to provide different clamp voltages for different polarity ESD events.

Growing community of inventors

Chandler, AZ, United States of America

Abhijat Goyal