Texas Instruments Corporation

Burr-brown Corporation

Abdullah Yilmaz

Ka Yin Leung

Jerry Doorenbos

Binan Wang

Hugo Cheung

Turker Kuyel

James Lee Todsen

Paul Thomas Frost

Aditya Vighnesh Ramakanth Bommireddipalli

Ruben Antonio Vasquez

A system includes a plurality of digital-to-analog converter (DAC) channels. Each DAC channel includes a current control circuit which receives a start limit signal or an end limit signal. The current control circuit reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system includes a controller which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.

Apparatus and method of over-current limit for multi-channel digital-to-analog converters

A digital-to-analog converter (DAC) for converting a digital input word to an analog output signal includes a string DAC, a first interpolator and a second interpolator. The string DAC outputs a first voltage and a second voltage in response to M most significant bits of the digital input word. The first interpolator interpolates between the first and second voltages in response to middle Q least significant bits of the digital input word and provides a first interpolated voltage. The second interpolator interpolates between the first interpolated voltage and the second voltage in response to lower P least significant bits of the digital input word.

Digital-to-analog converter with cascaded least significant bit (LSB) interpolator circuit

A segmented string digital-to-analog converter (DAC) comprises least significant bits (LSB subword) interpolation circuitry. The LSB subword interpolation circuitry defines, for each input digital word (or code), an offset voltage representative of an M bit LSB subword of the input digital word. The offset voltage modifies a coarse analog representation voltage of an N bit most significant bits (MSB subword) of the input digital word. The LSB subword interpolation circuitry includes a coarse analog representative voltage input, an LSB subword input, an LSB modification circuit, an offset voltage defining circuit, and a summation device. The DAC further includes a segmented string and a coarse level device connected to tap points of the segmented string. The offset voltage defining circuit receives an LSB subword and defines an offset voltage for modifying the corresponding coarse analog representative voltage. Such an offset voltage is defined based on a given modified LSB subword. The LSB modification circuit modifies the given LSB subword received via the LSB subword input, to create the given modified LSB subword. By modifying the LSB subword, errors introduced due to variations in the upper tap and lower tap voltage levels can be mitigated.

Integral nonlinearity error correction for interpolating string DAC

A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of semiconductor die area. A digital-to-analog converter includes a main DAC to be calibrated, a memory, a plurality of calibration DACs, and an analog summing circuit. The main DAC receives digital input code values, and converts the respective input code values into an analog signal. A first calibration DAC receives a predetermined number of lower order bits of the respective input code values, and interpolates between a positive reference voltage and a negative reference voltage to generate linear waveforms for the PWL approximation. A second calibration DAC generates the positive reference voltage, and a third calibration DAC generates the negative reference voltage. The memory stores a plurality of PWL breakpoint code values representing respective integral non-linearity error values of the main DAC, and applies consecutive PWL breakpoint code values to the second and third calibration DACs, respectively, to generate the positive and negative reference voltages for the first calibration DAC.

All-analog calibration of sting-DAC linearity: application to high voltage processes

An M&plus;N bit DAC includes an N-bit interpolation circuit for interpolating between a first voltage (Vhigh) on a first conductor ( A) and a second voltage (Vlow) on a second conductor ( B), an output amplifier ( ), a calibration interpolation circuit ( ), a memory circuit ( ) for storing error information corresponding to various values of the first voltage and second voltage, outputs of the N-bit interpolation circuit and the calibration interpolation circuit being coupled to inputs of the output amplifier, and switching circuitry responsive to a N-bit portion of a M&plus;N input word coupling the memory to inputs of the of the calibration interpolation circuit so as to correct integral nonlinearity errors associated with the various values of the first and second voltages.

Integral nonlinearity error correction circuitry and method for DAC

An input buffer circuit for use with an analog-to-digital converter is provided. The input buffer circuit comprises a first amplifier configured with a second amplifier to improve the overall gain of the input buffer circuit. The first amplifier comprises a differential pair of transistors configured with a second pair of transistors comprising a current mirror arrangement, wherein one of the differential pair of transistors of the first amplifier is configured in a diode-connected arrangement to provide a first feedback loop, while the second amplifier comprises a differential pair of transistors configured with another pair of transistors also comprising a current mirror arrangement, with the second amplifier and the current mirror arrangement of the first amplifier comprising a second feedback loop. Further, the first amplifier is configured such that the differential pair of transistors comprise different sized transistor devices, thus creating an offset voltage which permits the input voltage to swing close to ground, and which maintains the output voltage at voltage level higher than the input voltage by the amount of the offset voltage.

Input buffer for analog-to-digital convertor

Linearity of an n-bit integrated resistor string is improved by arraying the 2 resistors in 2 columns of 2 series coupled resistors each. The 2 columns of resistors are grouped in 2 groups of serially coupled columns of resistors with the total resistance of each group of columns of resistors substantially the same as the total resistance of each of the other groups of columns of resistors.

Resistor string integrated circuit and method for reduced linearity error

A segmented digital-to-analog converter includes a string DAC (,) and an interpolation DAC (,). The string DAC includes 2,series-connected string resistors (Ri) and 2,pairs of switches (Sia,b). The switch pairs couple a first (,) and second (,) conductor across each resister responsive to the MSB subword decoder (,). The interpolation DAC (,), responsive to the LSB subword decoder (,), connects an input of a plurality of differential stages to the first conductor (,) and second (,) conductor. Each differential stage includes a first transistor (Q,) and a second (Q,) transistor differentially coupled to a corresponding tail current source (I,). The drains of the first (Q,) and second (Q,) transistors are connected to a first load device (Q,) and second (Q,) load device and the inverting and non-inverting inputs of the output amplifier (,) via third (,) and forth (,) conductors, respectively.

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Tucson, AZ, United States of America

Abdullah Yilmaz