International Business Machines Corporation

Abdullah Serdar Yonar

Marcel A Kossel

Pier Andrea Francese

Mridula Prathapan

Thomas E Morf

Matthias Braendli

The invention is notably directed to a voltage-to-time converter comprising a first interleaving stage configured to perform a sampling of an input voltage, thereby generating a first set of sampled voltage signals. The first interleaving stage is further configured to perform a first voltage-to-time conversion in an interleaved manner, thereby generating a first set of time-interleaved signals in the time domain. A second interleaving stage is configured to perform a time-to-voltage conversion of the first set of time-interleaved signals, thereby generating a second set of sampled voltage signals. The second interleaving stage is further configured perform a second voltage-to-time conversion in an interleaved manner, thereby generating a second set of time-interleaved signals in the time domain. The invention further concerns a related design structure and a related method.

Time domain interleaving

A successive-approximation analog-to-digital converter includes a sampling circuit for sampling an analog input signal to acquire a sampled voltage, and a regenerative comparator for comparing the sampled voltage with a succession of reference voltages to generate, for each reference voltage, a decision bit indicating the comparison result. The converter also includes a digital-to-analog converter which is adapted to generate the succession of reference voltages, in dependence on successive comparison results in the comparator, to progressively approximate the sampled voltage. The regenerative comparator comprises an integration circuit for generating output signals defining the decision bits, and a plurality of regeneration circuits for receiving these output signals. The regeneration circuits are operable, in response to respective control signals, to store respective decision bits defined by successive output signals from the integration circuit.

Successive-approximation analog-to-digital converters

A hierarchical time step generator circuit is configured to be used for a time-based analog-to-digital converter. The hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal. The time-based analog-to-digital converter is configured to be controlled to digitize the input signal by the multiphase clock signals. The hierarchical time step generator includes a first level time step generator configured to generate the a set of first level multiphase signals in response to receiving the reference clock signal a phase interpolator circuit configured as second level to generate second level clock signals between each of the first level clock signals and a third level configured to generate the third set of multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of the second level clock signals.

Sampling circuit with a hierarchical time step generator

Disclosed herein is an analog-to-digital converter circuit configured for digitizing an analog input signal. The analog-to-digital converter comprises an analog input configured for receiving the analog input signal. The analog-to-digital converter circuit further comprises at least one sub-ADC connected to the analog input signal, wherein the at least one sub-ADC is configured to output at least one encoded output vector in response to receiving the analog input signal. The analog-to-digital converter circuit further comprises a lookup circuit comprising a nested lookup table. The lookup circuit is configured to select an output value from the nested lookup table using the at least one encoded output vector, wherein the lookup circuit is configured to provide the output value as the digitization of the analog input signal.

Analog-to-digital converter circuit with a nested look up table

A synchronous divider circuit with time-synchronized outputs. The synchronous divider circuit includes a plurality of divider stages including each a D-flip-flop circuit and a respective retiming flip-flop circuit, wherein an output terminal of the retiming flip-flop circuit of a current divider stage is connected to an input of the D-flip-flop circuit of a next divider stage, and wherein the current divider stage includes an additional retiming flip-flop circuit, wherein the output terminal of the retiming flip-flop circuit of the current divider stage is connected to an input terminal of the additional retiming flip-flop circuit of the current divider stage, so that an output signal of the additional retiming flip-flop circuit of the current divider stage and an output terminal of the retiming flip-flop circuit of the next divider stage are time-synchronized with respect to each other.

Synchronous divider based on cascaded retiming

A method of operating a wireline receiver. The receiver may include a front-end comparator and a feedback controller. The method may include providing, by the front-end comparator, a symbol signal by processing a received electrical input signal according to a tunable timing characteristic of the front-end comparator. The method may further include adapting, by the feedback controller, the processing of the input signal to match a predetermined processing criterion by tuning the timing characteristic based on the symbol signal.

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Zurich, Switzerland

Abdullah Serdar Yonar