Advanced Micro Devices Corporation

Globalfoundries Inc.

Abdullah Mohamad Yassine

Rama Rao Goruganthu

Ronald M Potok

Gregory A Dabney

Shannon B Smith

Kola Olasupo

Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An irradiation mask directs light or heat to a series of fractional portions of the surface to perturb portions of the plural circuit structures. The irradiation mask is adjustable such that at least one of the exposed series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip undergoes a test pattern during the irradiation to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions. Multiple paths can be tested simultaneously to inform subsequent individual CTP path tests.

Wide area soft defect localization

Various methods and apparatus for electrically probe testing a semiconductor chip with circuit perturbation are disclosed. In one aspect, a method of testing is provided that includes contacting a first nano probe to a conductor structure on a first side of a semiconductor chip. The semiconductor chip has plural circuit structures. A external stimulus is applied to a selected portion of the first side of the semiconductor chip to perturb at least one of the plural circuit structures. The semiconductor chip is caused to perform a test pattern during the application of the external stimulus. An electrical characteristic of the semiconductor chip is sensed with the first nano probe during performance of the test pattern.

Method and apparatus for nano probing a semiconductor chip

Semiconductor device analysis is improved through the distinguishing of gate oxide failures from other non-oxide failures. According to an example embodiment of the present invention, oxide failures are distinguished from non-oxide shorts between a gate and source/drain region in a semiconductor device during gate oxide analysis. An electrical characteristic that exhibits a first response to an oxide failure and a second response to a non-oxide failure is detected and used to detect the nature of a short in the device. This analysis is easily incorporated into other tests, such as the Voltage Ramp Dielectric Breakdown test (VRDB), and is particularly useful for improving the ability to detect and analyze defects without necessarily viewing the defect or destroying the device.

Growing community of inventors

Austin, TX, United States of America

Abdullah Mohamad Yassine