Silicon Laboratories Inc.

Other

Abdulkerim Coban

Mustafa H Koroglu

Alessandro Piovaccari

Ramin Khoini-Poorfard

Aslamali A Rafi

David S Trager

Wenhuan Yu

Vitor Pereira

Ruifeng Sun

Rangakrishnan Srinivasan

John M Khoury

Michael Johnson

Clayton H Daigle

Pio Balmelli

Francesco Barale

Zhongda Wang

Sriharsha Vasadi

James T Kao

András Vince Horvath

Péter Onódy

Ravi Kishore Kummaraguntla

Krishna Pentakota

Alan F Hendrickson

Yu Su

Pascal Blouin

Emmanuel Gautier

David Le Goff

Ramin Khoini Poorfard

Sanjeev Suresh

Fabrice Portier

A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to amplify the delayed oscillating signal for transmission sufficient to produce interference, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

System and method of mitigating interference caused by coupling from power amplifier to voltage-controlled oscillator

In one embodiment, a method includes: setting, via a controller of a receiver, a plurality of gain components of the receiver for a maximum gain setting for an automatic gain control (AGC) sensitivity (SENS) mode; receiving, in a controller of the receiver, an indication that a power level of an intermediate frequency (IF) signal measured at an output of an IF amplifier of the receiver exceeds a first threshold; and transitioning from an AGC SENS mode to an AGC adjacent channel interference (ACI) mode in response to the indication that the power level of the IF signal exceeds the first threshold.

Gain contol to optimize sensitivity and blocking performance

A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to use the delayed oscillating signal for transmitting a signal, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

In one embodiment, an apparatus includes a clock generator circuit to receive a first clock signal at a first frequency and output a second clock signal at a second frequency less than the first clock frequency. The clock generator circuit may include: a divider circuit to divide the first clock signal to obtain at least a first divided clock signal and a second divided clock signal; and a gating circuit coupled to the divider circuit, the gating circuit to gate the first clock signal with at least one of the first divided clock signal and the second divided clock signal to output the second clock signal.

Clock generator circuit for generating duty cycle clock signals at low power

In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.

Providing a programmable inductor to enable wide tuning range

A voltage reference circuit that can operate in a large supply voltage range with high PSRR, that dissipates low-power for a given output noise, and that has a low temperature-coefficient (TC) across a wide-temperature range. The voltage reference circuit does not require any calibration for low TC and high PSRR, occupies a relatively small circuit area, may be used without additional supply filtering in noisy or high-ripple supply environments, and is more robust against device mismatch effects particularly compared to designs based on sub-threshold operations. The voltage reference circuit is a special form of constant transconductance circuit that uses current mirror ratios that are chosen to achieve high PSSR and low noise properties. The device saturation voltage may be chosen so that flat temperature characteristics may be achieved.

Voltage reference circuit

A continuous-time (CT) delta-sigma modulator (DSM) based analog to digital converter (ADC) in a radio receive chain supports a wide range of data rates in a power efficient way in a small die area. The ADC utilizes a 2order loop-filter with a single-amplifier loop-filter topology using a two stage Miller amplifier with a feed forward path and a push-pull output stage. High bandwidth operations utilize a 'negative-R' compensation scheme at the amplifier input. Negative-R assistance is disabled for low data rate applications. With the negative-R assistance disabled, loop-filter resistor values are increased, instead of only the loop filter capacitor values to scale the noise transfer function (NTF), thereby limiting the capacitor area needed and enabling lower power operation. The NTF zero location is programmable allowing the NTF zero to be located near the intermediate frequency for different bandwidths to reduce the DSM quantization noise contribution for narrow-band (low data rate) applications.

Low-power programmable bandwidth continuous-time delta sigma modulator based analog to digital converter

A calibration operation adjusts a frequency of a ring oscillator to a desired frequency by adjusting programmable RC circuits in the stages of the ring oscillator. The programmable RC circuits have programmable capacitors, resistors, or both. The RC circuits account for most of the delay through the ring oscillator. Another circuit with its own RC time constant is calibrated based on the adjustments made to the RC circuits in the ring oscillator to achieve the desired frequency.

Ring oscillator based RC calibration circuit

A unity gain buffer is shared by a charge pump and an active loop filter in a phase-locked loop. The charge pump uses the unity gain buffer to reduce current mismatch in the charge pump and the active loop filter uses the unity gain buffer in a circuit that increases the effective capacitance of the active loop filter.

Charge pump and active loop filter with shared unity gain buffer

In one form, an analog-to-digital converter (ADC) includes first and second ring-oscillator ADCs, a modulus subtractor, and a decimation filter. The first and second ring-oscillator ADCs are responsive to true and complement input voltages, respectively, have outputs for providing first and second digital phase signals, respectively, each having a first predetermined number of bits sampled at a first frequency. The modulus subtractor subtracts the second digital phase signal from the first digital phase signal to provide a phase difference signal. The decimation filter differentiates the phase difference signal at a second frequency lower than said the frequency to provide a frequency signal proportional to a differential voltage between the true input voltage and the complementary input voltage, and decimates the frequency signal to provide a digital code having a second predetermined number of bits greater than the first predetermined number of bits.

Efficient voltage controlled oscillator (VCO) analog-to-digital converter (ADC)

A phased-locked loop (PLL) includes a first oscillator supplying a first oscillator signal with a first jitter component and a second oscillator supplying a second oscillator signal with a second jitter component. The second jitter component is higher than the first jitter component. A selector circuit selects either the first oscillator signal or the second oscillator signal as the PLL output signal. The first oscillator signal and the second oscillator signal may have different frequencies with the lower frequency signal having more jitter. The oscillator producing the signal with less jitter utilizes more power. A continuous time delta-sigma modulator analog-to-digital converter (ADC) receives the PLL output signal as an input clock signal. A high gain setting of an amplifier supplying an input signal to the ADC selects a lower jitter signal input clock signal and a lower gain setting selects a higher jitter input clock signal.

PLL for continuous-time delta-sigma modulator based ADCs

A communications receiver with improved blocker performance including multiple gain tables selected based on a number of reductions or back offs from a maximum coarse gain setting. A receiver chain with multiple gain stages converts a received signal to a digital format, determines the power level of the received signal, and provides an overload indication. A first gain table maximizes SNR and SNDR for weak blockers and at least one additional gain table successively improves SNDR for stronger blockers. An AGC circuit initially sets the coarse gain setting to maximum, and backs off a number of coarse gain steps until the receiver chain is not overloaded. The number of back off steps is used to select a gain table, the power level is used to select an entry in the selected table, and the selected entry includes gain settings for the gain stages of the receiver chain.

Automatic gain control system and method with improved blocker performance

In one example, a method includes: at a beginning of a packet communication, setting a maximum gain setting for a plurality of gain components of a receiver; and during a preamble portion of the packet communication, reducing a gain setting for one or more of the plurality of gain components in response to at least one of a first signal output by a first component of the receiver being greater than a first threshold and a second signal output by a second component of the receiver being greater than a second threshold.

System, apparatus and method for performing automatic gain control in a receiver for a packet-based protocol

A peak detector including an input circuit with five same-sized transistors, in which four of the input transistors are coupled in parallel between a control node and a bias node and receive a corresponding one of two in-phase signals and two quadrature signals. The fifth transistor is coupled between a current node and the bias node and has its control terminal coupled to an output node. A bias circuit establishes a predetermined bias current that flows through the five input transistors. A current mirror mirrors the current through the fifth transistor from the current terminal into the four parallel-coupled input transistors via the control node. An output circuit charges a peak capacitor based on voltage developed at the control terminal of the fifth transistor. The peak detector is low power and compact and detects the actual peak of the input signal with greater accuracy compared to a conventional peak detector.

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Austin, TX, United States of America

Abdulkerim Coban