Sundstrand Corporation

Abdul Rashid

Joseph E Foster

Barry T Drager

Walter Fry

Joe Foster

David Hatten

The problems of minimizing size and weight in aircraft and avoiding requirements for custom design are minimized in a digital voltage regulator circuit (120). The circuit (120) includes a programmed processor circuit (124) having a memory circuit (138), and a drive circuit (132) operatively coupled with the processor circuit (124) for developing an exciter control signal. This circuit (120) is manufactured using custom very large scale integration (VLSI) technology to reduce size, weight, life cycle costs and improve reliability.

Digital voltage regulator

The problem for distributing load equally between multiple generators (34) in multi-channel generating systems is resolved using a voltage regulator (60) including a reactive load division loop (84) and real load division loop (86). The voltage regulator (60) controls generator excitation responsive to sensed voltage. The reactive load division loop and real load division loop modify the voltage regulator output to divide loading equally between each generator.

Voltage regulator load division using real and reactive generator output

The frequency of the signal is determined by counting the period of the signal. A round-off circuit increments the count if the end of the signal occurs after the midpoint between counts.

Frequency counter with round off function

A 'reversible master/slave' handshaking protocol is disclosed for addressing the problem of interfacing a multiplexing analog-to-digital (A/D) converter, having a first operating rate, to a microprocessor, having a second operating rate. In the specific embodiment of a generator control unit (GCU) for an electrical power generating system, an analog multiplexer (124), an A/D converter (126), and a dual-port RAM (130) are controlled by an A/D controller (134) to provide data words to a voltage regulator processor (92). If a fast A/D converter is used, then the A/D controlling system will multiplex and convert samples from all of the analog input signals, load the RAM, and wait for the processor to read the RAM. If the A/D conversion rate is slow, the A/D controller will continuously sample all the multiplexed channels, while the processor waits for the appropriate channel information to be loaded into the RAM. In this manner, data acquisition can be perform utilizing A/D converters having various conversion rates, multiplexers having additional channels, or microprocessors having numerous feedback control loops.

Multiplexing A/D converter for a generator control unit

A noise filter for the zero crossing detector of a digitized sine wave signal uses an adjustable noise integrator. The noise integrator incorporates a counter. The integration characteristic of the counter is adjustable by selecting a count rate or a count limit from a microprocessor memory.

Noise filter for zero crossing detector

The problem of adusting a digital reference value without modifying a program or stored memory values in a voltage regulator (60) is minimized using an analog signal generator (114). A reference loop (110) which determines a desired point of regulation voltage level receives a trim value from the analog signal generator (114) to adjust a stored reference value (112) to offset the same.

Reference trimming for a digital voltage regulator

The problem of stabilizing operation of a load division control (74) is resolved using a phase angle counter circuit (90) which calculates phase angle insensitive to frequency changes of the output voltage waveform. The phase angle counter circuit (90) includes a series of counters (94, 96, 100 and 102) for calculating phase angle.

Frequency insensitive digital phase angle measuring circuit

The problems of modifying and/or fine tuning current limit in a voltage regulator are minimized using a programmable current limit. The programmable current limit provides for storage of multiple reference values in a processor memory to provide different rates of current limit control.

Programmable current limit curve

This invention relates to a method of testing an n-bit programmable counter. It is desired to test the n-bit programmable counter in fewer than 2.sup.n cycles. Accordingly, a counter value output on the counter is coupled to a variable increment rate input on the counter. Each bit of the counter is reset to a binary 0 initial state. A binary 1 state is loaded into a carry-in bit of the counter and the counter is iteratively doubled, by means of the coupling between the counter value output and the variable increment rate input, until a carry-out bit of the counter assumes the binary 1 state to thereby allow the counter to be fully tested in n+1 iterations. The counter value output and the variable increment rate input are decoupled from the counter when the counter is not being tested. The counter is provided with a parallel load input to allow simultaneous resetting of each bit. Intermediate counter values may be checked to provide a means for localizing errors within the counter.

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Rockford, IL, United States of America

Abdul Rashid