Actel Corporation, Inc.

Other

Advanced Micro Devices Corporation

Abdul R Forouhi

John L McCollum

Yeouchung Yen

Chenming Hu

Steve S Chiang

Frank W Hawley

John Durbin Husher

Wenn-Jei Chen

Esmat Z Hamdy

Abdelshafy A Eltoukhy

Iton Wang

Shih-Oh Chen

Bert L Allen

Yeochung Yen

Iris L Bloomer

Yeouchung Yan

A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures. A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.

Circuits for ESD Protection of metal to-metal antifuses during processing

According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers. According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage. According to a third aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer disposed over a plug of an electrically conductive material disposed between two metallization layers.

Fabrication method for metal-to-metal antifuses incorporating a tungsten

An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first metal electrode, a first antifuse dielectric layer, preferably silicon nitride, disposed on the lower first electrode and an antifuse layer, preferably amorphous silicon, disposed on the first dielectric layer. An inter-layer dielectric layer is disposed on the antifuse layer and includes an antifuse via formed completely therethrough. A second antifuse dielectric layer, preferably silicon nitride, is disposed over the amorphous silicon layer in the antifuse via, and an upper second metal electrode is disposed over the second dielectric layer in the antifuse via.

Electrically programmable antifuse incorporating dielectric and

Above via metal-to-metal antifuses incorporating a tungsten via plug

A metal-to-metal antifuse comprises a lower electrode comprising a first metal layer in an integrated circuit, a first barrier layer formed from a layer of TiW:N disposed over the lower electrode, a layer of antifuse material formed from amorphous silicon over the first barrier layer, a second barrier layer formed from a layer of TiW:N disposed over the layer of antifuse material, said second barrier layer, and an upper electrode over the second barrier layer, the upper electrode comprising a second metal layer in the integrated circuit.

Method of fabricating metal-to-metal antifuse with improved diffusion

In an antifuse and metal interconnect structure in an integrated circuit a substrate has an insulating layer disposed on an upper surface, a first multilayer metal interconnect layer disposed on the insulating layer, and having a first portion forming a lower antifuse electrode and a second portion forming a lower metal interconnect electrode wherein the first portion includes an upper barrier metal layer. An inter-metal dielectric layer is disposed on the lower antifuse and metal interconnect electrodes wherein the inter-metal dielectric layer includes an antifuse via formed therethrough and communicating with said lower antifuse electrode, and a metal interconnect via former therethrough communicating with the lower metal interconnect electrode, An antifuse material layer is disposed in the antifuse via, and a second multilayer metal interconnect layer is disposed on the antifuse material layer and in the upper metal interconnect electrode via and on the lower metal interconnect electrode.

Electrically programmable antifuse

According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers, According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage. According to a third aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer disposed over a plug of an electrically conductive material disposed between two metallization layers.

Metal-to-metal antifuse with conductive

An antifuse according to the present invention includes a lower electrode formed from a first metal interconnect layer in an integrated circuit or the like. The lower electrode is disposed on an insulating surface. An inter-metal dielectric including an antifuse aperture disposed there lies over the inter-metal dielectric layer. The antifuse aperture extends through the inter-metal dielectric layer and also extends completely through the lower electrode. An antifuse material is disposed in the antifuse aperture. An upper electrode formed from a first metal interconnect layer is disposed over the antifuse material.

Electrically programmable antifuse element

Circuits for ESD protection of metal-to-metal antifuses during processing

Metal-to-metal antifuse with improved diffusion barrier layer

A process for fabricating the metal-to-metal antifuse of the present invention includes the steps of forming a first metal layer on a semiconductor or other microcircuit structure; forming a first barrier layer over the first metal layer; forming a thick insulating layer over the barrier layer; forming an antifuse aperture in the thick insulating layer; forming a first heavily doped amorphous silicon layer in the aperture over the first barrier layer; forming a dielectric antifuse material layer over the first amorphous silicon layer; forming a second heavily doped amorphous silicon layer over the first dielectric antifuse material layer; forming a second barrier layer over the second amorphous silicon layer; and forming a second metal layer over the second barrier layer.

Low-temperature process metal-to-metal antifuse employing silicon link

An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first electrode, a first dielectric layer disposed over the lower first electrode, a layer of amorphous silicon disposed above the first dielectric layer, a second dielectric layer disposed above the amorphous silicon layer, and an upper second electrode disposed above the second dielectric layer.

A metal-to metal antifuse device is provided in a double layer metal interconnect structure. A lower electrode comprises a first multilayer metal layer interconnect disposed on an insulator. An inter-metal dielectric is disposed on the first metal layer interconnect having an antifuse via. An antifuse material layer is disposed in the antifuse via and having an upper electrode comprising a second multilayer metal layer interconnect.

Growing community of inventors

San Jose, CA, United States of America

Abdul R Forouhi