General Electric Company

Electric Power Research Institute Incorporated

Abdallah Mahmoud Itani

Nick Andrew Van Stralen

Stephen Michael Hladik

John Anderson Fergus Ross

Robert Gideon Wodnicki

Victor D Roberts

Peter W Dietz

Gerald J Carlson

William Thomas Hatfield

Philip H Peters, Jr

William Macomber Leue

John Anderson Ross

A turbo decoder control comprises an address generator for addressing systematic data, parity data, and systematic likelihood ratios according to a pre-determined memory mapping. The systematic data samples are accessed in the order required by the MAP decoding algorithm such that interleaving and de-interleaving functions in the MAP decoding algorithm are performed in real-time, i.e., without delay. Such memory-mapping in combination with data handling functions (e.g., multiplexing and combinatorial logic) minimizes memory requirements for the turbo decoder and allows for use of programmable interleavers, variable block lengths, and multiple code rates.

Turbo decoder control for use with a programmable interleaver, variable block length, and multiple code rates

A turbo decoder system utilizing a MAP decoding algorithm has a predetermined number of turbo decoder modules for decoding segments of a turbo code component code word in parallel, thereby expanding the block-length and data rate capability of the turbo decoder. Upon completion of any half iteration of the MAP decoding algorithm, the a posteriori bit probability estimates are provided to an interleave/de-interleave-and-convert-data function block wherein they are re-ordered, segmented, used to modify the original received data samples, and provided back to the respective turbo decoder modules as input data samples for the systematic bits. Decoding continues in this manner until a predetermined number of half iterations is performed, and data decisions are made on the final a posteriori estimates.

Turbo decoder with modified input for increased code word length and data rate

A turbo decoder system utilizing a MAP decoding algorithm has a predetermined number of turbo decoder modules for decoding segments of a turbo code component code word in parallel, thereby expanding the block-length and data-rate capability of the turbo decoder system. Input data samples are provided to an interleaver/de-interleaver module wherein they are divided into segments of predetermined size, each segment being provided to a respective turbo decoder module. The outputs of each turbo decoder module are a posteriori probabilities which are re-ordered in the interleaver/de-interleaver module, segmented, and provided back to the turbo decoders as a priori information-bit probabilities. For the case of a turbo code comprising two component codes, the a posteriori information-bit probabilities are re-ordered according to the interleaver definition at the end of odd-numbered half iterations, while at the end of even-numbered half iterations, they are re-ordered according to the de-interleaver definition. Decoding continues until the desired number of iterations have been performed. Data decisions are made on the final a posteriori bit probability estimates.

Modular turbo decoder for expanded code word length

A high-speed turbo decoder utilizes a MAP decoding algorithm and includes a streamlined construction of functional units, or blocks, amenable to ASIC implementation. A gamma block provides symbol-by-symbol a posteriori state transition probability estimates. Two gamma probability function values are provided via selection switches to the alpha and beta blocks for calculating the alpha and beta probability function values, i.e., performing the alpha and beta recursions, respectively, in parallel, thus significantly increasing decoding speed. A scaling circuit monitors the values of the alpha and beta probability functions and prescribes a scale factor such that all such values at a trellis level remain within the precision limits of the system. A sigma block determines the a posteriori state transition probabilities (sigma values) and uses the sigma values to provide soft-decision outputs of the turbo decoder.

High-speed turbo decoder

Forward and backward recursive calculations in a maximum a posteriori decoding process are performed in parallel processes, rather than sequentially, allowing the a posteriori transition probabilities to be calculated in the same time interval as the recursions, thereby reducing decoding latency and required memory.

Maximum A posterior estimator with fast sigma calculator

Methods and apparatus for generating test vectors for use in testing ASIC designs at both the functional and circuit levels, and for comparing the results of functional level and circuit level tests, employ a set of software tools to facilitate generating test vectors and to compare results of simulation at the functional level with results of simulation at the synthesized circuit level. The software tool set includes a preprocessor program which reads source files and produces skeleton test vector files, a compiler program for compiling the test vector files, and an output comparison program for comparing functional level test results with circuit simulation level test results.

Methods and apparatus for generating test vectors and validating ASIC

A method and apparatus for protecting switching elements, and in particular, thyristor switching elements, which are used to supply pulses to a capacitive load, from damage resulting from false triggering signals, i.e., triggering signals not accompanied by actual sparkover conditions in the load. Since termination of normal pulse cycles in such pulser systems are accomplished by a return to high forward voltage across the switching elements, false triggers generated closely prior to such termination and within the forward recovery time of a thyristor switching element present a danger that the termination of a normal cycle will result in a weak turn-on and consequent damage of the switching element. By insuring that all such potentially false triggers have a duration which extends past termination of the pulse cycle damage to the switching element resulting from such false triggers is inhibited.

False triggering protection for switching device of a capacitive load

A method and apparatus for protecting switching elements, and in particular, thyristor switching elements, which are used to supply pulses to a capacitive load, from damage resulting from sparkover occurring in that load are described. The load voltage pulse is characterized by a period of rising voltage followed by a period of falling voltage, these two periods being separated by a transition period of maximum vulnerability of the switching element to damage from sparkover. Specifically, during this period of maximum vulnerability of the switching elments to damage, a gate trigger pulse is applied to the elements to cause them to resume a conductive state, independent of the occurrence of an abnormal sparkover condition.

Protection arrangement for switching device of a capacitive load pulser

A gas discharge lamp is started with a high frequency AC signal from an oscillator and then operates on a low frequency AC signal provided by an AC to AC converter synchronously with the AC supply line. The low voltage switching devices of the converter are protected from the high voltages of the high frequency oscillator by locking the converter in a single phase during starting.

Electronic ballast with low frequency AC to AC converter

The switches of an AC to AC converter are switched synchronously with the AC supply voltage. EMI conducted to the AC power line is greatly reduced since the rectifier diodes are off at the time of switching, thus avoiding undesirable effects on nearby electrical apparatus. The converter is useful in a ballast for a discharge lamp.

Driver circuit controller for AC to AC converters

A method for simultaneously triggering a plurality of serially connected SCR's transfers energy from a relatively low voltage energy source to each of a plurality of energy storage devices which are coupled respectively to the gate of a corresponding SCR through a respective switching device. The energy from each storage device is simultaneously discharged into the gate of each respective SCR by a respective trigger signal from the low voltage energy source to each respective switching device. Apparatus for simultaneously triggering a plurality of serially connected SCR's comprises a pulse transformer for transferring energy from a relatively low voltage source of energy.

Means and method for simultaneously triggering series SCR's

A fault location system for use with sealed, gas-insulated electrical power apparatus. The system includes a sensor for placement in close proximity to the outer surface of a housing of the apparatus and a detector for in-place reading of the sensor. The detector comprises a first fluxgate magnetometer for detecting magnetization of the sensor. A second fluxgate magnetometer is positioned adjacent and parallel to the first magnetometer to detect only the background magnetic field. An alternating current electrical signal is applied to the magnetometers. A direct current is then automatically generated wherein the direct current is a function of the even harmonics of the ac output of the second magnetometer. The direct current is used to cancel the effects of the background magnetic field detected by the second magnetometer. As such, the direct current is applied to the first magnetometer to cancel the effects of the background magnetic field therefrom.

System for reading magnetic sensors for fault location in gas-insulated

Four switching elements are configured to reduce the voltage of either an alternating or a direct current electrical power source. The present circuit effectively operates like a variable autotransformer when used with a.c. input power. Additionally, when employed with a conventional resistive load, the present invention exhibits a power factor near unity.

Pulse modulated electronic voltage controller with smooth voltage output

A data transmission system and method is provided for transferring digital information which has been converted to a multiframe format of serial bits over a single optical cable. The mutliframe format used by the system includes sequential data frames each containing a sequence of bits at a bit frequency, of which a certain number are data bits containing the digital information. The data frames are transferred by way of the optical cable to a receiver. In the receiver a clock signal is generated by a variable oscillator which operates at a frequency substantially equal to the bit frequency. Circuitry responsive to the bits maintains a predetermined phase relationship between the clock signal from the oscillator and the bits. Decoder circuitry receives the transmitted bits and decodes the bits to retrieve the digital information using the clock signal from the oscillator. The method of retrieving the digital information from the above-described multiframe format, after having been transferred over the single optical cable, includes the following steps: A clock signal is generated having a frequency substantially equal to the bit frequency. A predetermined phase relationship is maintained between the clock signal and the bits. The clock signal is then used to select the data bits from the sequence of bits in the data frames and to retrieve the digital information from the data bits.

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Ballston Spa, NY, United States of America

Abdallah Mahmoud Itani