Juniper Networks, Inc.

Apple Inc.

Netlogic Microsystems, Inc

Rmi Corporation

Broadcom Corporation

Abbas Rashid

Nazar A Zaidi

David T Hass

Mark Bryers

Jerome Francis Duluk, Jr

Richard E Hessel

Fred Gruner

Abraham Mammen

Bo Hong

Joseph P Grass

Elango Ganesan

Michael Freed

Ramesh Panwar

Robert G Hathaway

Frederick R Gruner

Ricardo Ramirez

Yen C Lee

Sankar Ramanoorthi

Mark Vilas

John Phillips

Yuhong Zhou

Gregory G Spurrier

Jason Rupert Redgrave

Tuan Anh Nguyen

Joseph P Bratt

Emerson S Fang

Sushma Shrikant Trivedi

Vaughn Todd Arnold

Jack Benkual

Sidong Li

Shun Wai Go

Stephen L Dodgen

Hengwei Hsu

Matthew N Papakipos

George Cuan

Sam Ng

Nathan D Tuck

Zhaoyu Gong

Chau Anh Ngoc Nguyen

Lindy Fung

Albert Suan-Wei Tsay

Thomas Y Ho

Chau Ahn Ngoc Nguyen

Thomas Y Yo

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Advanced processor with fast messaging network technology

Advanced processor with interfacing messaging network to a CPU

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Content service aggregation system

A method and system are provided for performing efficient and effective scheduling in a multi-threaded system. Dynamic control of scheduling is provided, in which priority weights can be assigned for some or all of the threads in the multi-threaded system. The priority weights are employed to control prioritization of threads and thread instructions by a scheduler. An instruction count for each thread is used in combination with the priority weights to determine the prioritization order in which instructions are fetched and assigned to execution units for processing.

Weighted instruction count scheduling

Advanced processor scheduling in a multithreaded system

Advanced processor with mechanism for fast packet queuing operations

A cross-bar switch includes a set of input ports to accept data packets and a set of sink ports in communication with the input ports to forward the data packets. Each sink port includes a communications link interface with a Retry input. When a signal is asserted on the Retry input, the sink port aborts transmission of a data packet and waits a predetermined period of time to retransmit the data packet.

Cross-bar switch incorporating a sink port with retry capability

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Deferred shading graphics pipeline processor having advanced features

A cross-bar switch includes a set of input ports for receiving data packets and a set of sink ports for transmitting the received packets to identified targets. A set of data rings couples the input ports to the sink ports. Each sink port utilizes the set of data rings to simultaneously accept multiple data packets targeted to the same destination&#x2014;creating a non-blocking cross-bar switch. Sink ports are also each capable of supporting multiple targets&#x2014;providing the cross-bar switch with implicit multicast capability.

Cross-bar switch having bandwidth allocation

Advanced processor messaging apparatus including fast messaging ring components configured to accomodate point-to-point transfer of non-memory related messages

Advanced processor with scheme for optimal packet flow in a multi-processor system on a chip

Advanced processor with system on a chip interconnect technology

Growing community of inventors

Fremont, CA, United States of America

Abbas Rashid