Xilinx, Inc.

Sanmina Corporation

Brixham Solutions Ltd.

Oracle International Corporation

Saratoga Speed, Inc.

Abbas Morshed

Sagheer Ahmad

Ygal Arbel

Jan Medved

Krishnan Srinivasan

Yijun Xiong

Fong Liaw

John Z Yu

Sharad Mehrotra

Aman Gupta

Jon Livesey

Eun Mi Kim

Christopher Youngworth

Thomas Gourley

Chuan-Wen George Tsang

John E Watkins

Elisa Rodrigues

Balakrishna Jayadev

Julian Ratcliffe

Shishir Kumar

Some examples described herein provide for an encrypted data quantization apparatus and method, for example a memory controller to quantize encrypted data using a cache. One or more embodiments includes obtaining a first set of plaintext data bits to be stored in a memory device using an encryption scheme. A memory address for encrypted data bits to be stored in the memory device is identified for a first subset of plaintext data bits. A second set of plaintext data bits associated with the memory address is obtained from a cache, if present. The second set of plaintext data bits are modified according to the first set of plaintext data bits to be stored in the memory device to generate a third set of plaintext data bits that are then encoded according to the encryption scheme for storage in the memory device.

Memory controller cryptographic data quantization using a cache

Examples herein describe techniques for method of accessing encrypted data. The techniques include receiving, via a memory controller, a first memory request to a first memory region, where the first memory region is encrypted based on a first key, and incrementing, based on the first memory request, a first counter associated with the first key. The techniques further include, in response to determining that the first counter exceeds a first threshold, initiating a key rolling operation to cause the first memory region to be encrypted based on a second key. The techniques further include tracking an address range of the first memory region that has been encrypted based on the second key, and, in response to determining that an address of a second memory request is outside of the address range, causing the second memory request to be completed based on the first key.

Key management system

Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.

NoC buffer management for virtual channels

Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

Dynamically allocated buffer pooling

Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.

Systems and methods to transport memory mapped traffic amongst integrated circuit devices

Embodiments herein describe an integrated circuit that includes a network on chip (NoC) where an egress logic block or switch performs a route lookup for a subsequent (e.g., downstream) switch in the NoC (referred to herein as look-ahead routing). After receiving the packet and a port ID from the egress logic block or the switch, the downstream switch knows, without performing route lookup of its own, on which port it should forward the packet. Thus, if the downstream switch performs other functions that are dependent on knowing the destination port (e.g., arbitration or QoS updating), the downstream switch can perform those functions immediately since the port ID was already determined by, and received from, the previous network element.

Distributed look-ahead routing in network-on-chip

Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.

Localized NoC switching interconnect for high bandwidth interfaces

Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.

NoC relaxed write order scheme

A network on a chip (NOC) peripheral interface (NPI) includes an NPI root, a plurality of switches coupled to the NPI root, and a plurality of NPI protocol blocks coupled to the plurality of switches. The NPI root, the plurality of switches, and the plurality of NPI protocol blocks are configured to route signals received from a master to a plurality of circuit blocks. A non-service command is routed to an intended circuit block of the plurality of circuit blocks. A switch of the plurality of switches or an NPI protocol block of the plurality of NPI protocol blocks generate a response message for a service command query with the destination address associated with the intended circuit block that is received from the master instead of routing the service command query to the intended circuit block.

NOC peripheral interconnect interrogation scheme

A system is provided comprising: a packet routing network; Flash storage circuitry; a management processor coupled as an endpoint to the network; an input/output (I/O) circuit coupled as an endpoint to the network; a packet processing circuit coupled as an endpoint to the network; a cache storage circuit coupled to send and received packets to and from the packet processing circuit; and a RAID management circuit coupled as an endpoint to the network and configured to send and receive packets to and from the Flash storage circuitry; wherein the management processor is configured to determine routing of packets among the I/O circuit, packet processing circuit and RAID management circuit; and wherein the packet processing circuit is configured to control cache read requests, cache write requests and cache data eviction.

Network system with cache offload service for flash storage

A system comprises a first host device, a second host device, and first and second cache controllers. A cache controller includes a cache memory interface, a first peripheral interface that communicates with the first host device, a second peripheral interface that communicates with the second host device, logic circuitry that loads a cache command from a cache command memory of the first host device, loads a cache command from a cache command memory of the second cache controller, and performs the cache commands, and error checking circuitry that detects an uncorrectable error in a first cache controller/memory pair and indicates the uncorrectable error condition to at least one of the first and second host devices. At least one of the first host device or the second host device writes contents of the cache memory of the second cache controller/memory pair to a main memory in response to the indication.

System and method for cache data recovery

A system comprises a first cache controller and at least a second cache controller. The first cache controller and the second cache controller each include a cache memory interface, an inter-cache controller communication link configured for bidirectional communication with the other cache controller, a first peripheral interface, a second peripheral interface, and logic circuitry. The first peripheral interface communicates with a first host device and the second peripheral interface communicates with a second host device. The first host device and the second host device are each connected to the first and second cache controllers by the first and second peripheral interfaces. The logic circuitry loads a cache command from a cache command memory of the first host device, loads a cache command from a cache command memory of the second cache controller, and performs the cache commands.

Cache memory management system and method

A system is provided comprising: a packet routing network; Flash storage circuitry; a management processor coupled as an endpoint to the network; an input/output (I/O) circuit coupled as an endpoint to the network; a packet processing circuit coupled as an endpoint to the network; and a RAID management circuit coupled as an endpoint to the network and configured to send and receive packets to and from the Flash storage circuitry; wherein the management processor is configured to determine routing of packets among the I/O circuit, packet processing circuit and RAID management circuit.

Network system with offload services for flash storage

A system and method are disclosed for processing a packet. Processing the packet comprises receiving the packet; translating the packet from a first protocol-specific format to a canonical packet format; translating the packet from the canonical packet format to a second protocol-specific format; and forwarding the packet.

Method for performing protocol translation in a network switch

A system comprises a host device and a cache controller. The host device includes a command buffer and a host application that posts a cache command that includes a cache key and a key aging alias in the command buffer. The cache controller includes logic circuitry configured to load the cache command from the command buffer of the first host device into the buffer memory, identify a match, if any, for the cache key in the command queue, perform the cache command, and return cache completion status information to the first host application, wherein the cache completion status information includes a value of the key aging alias in cache metadata when a match for the cache key is found and includes a value of the key aging alias provided by the first host application when a match for the cache key is not found.

Growing community of inventors

Los Altos, CA, United States of America

Abbas Morshed